[Mesa-dev] [PATCH 1/2] ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHERE

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_debug.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 src/amd/common/sid.h      |  1 +
 2 files changed, 47 insertions(+)

diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index a8f81bf..79473ec 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -213,20 +213,66 @@ static uint32_t *ac_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
 	case PKT3_EVENT_WRITE:
 		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
 			    S_028A90_EVENT_TYPE(~0));
 		print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
 		print_named_value(f, "INV_L2", (ib[1] >> 20) & 0x1, 1);
 		if (count > 0) {
 			print_named_value(f, "ADDRESS_LO", ib[2], 32);
 			print_named_value(f, "ADDRESS_HI", ib[3], 16);
 		}
 		break;
+	case PKT3_EVENT_WRITE_EOP:
+		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
+			    S_028A90_EVENT_TYPE(~0));
+		print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
+		print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 0x1, 1);
+		print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 1);
+		print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 1);
+		print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
+		print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
+		print_named_value(f, "ADDRESS_LO", ib[2], 32);
+		print_named_value(f, "ADDRESS_HI", ib[3], 16);
+		print_named_value(f, "DST_SEL", (ib[3] >> 16) & 0x3, 2);
+		print_named_value(f, "INT_SEL", (ib[3] >> 24) & 0x7, 3);
+		print_named_value(f, "DATA_SEL", ib[3] >> 29, 3);
+		print_named_value(f, "DATA_LO", ib[4], 32);
+		print_named_value(f, "DATA_HI", ib[5], 32);
+		break;
+	case PKT3_RELEASE_MEM:
+		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, ib[1],
+			    S_028A90_EVENT_TYPE(~0));
+		print_named_value(f, "EVENT_INDEX", (ib[1] >> 8) & 0xf, 4);
+		print_named_value(f, "TCL1_VOL_ACTION_ENA", (ib[1] >> 12) & 0x1, 1);
+		print_named_value(f, "TC_VOL_ACTION_ENA", (ib[1] >> 13) & 0x1, 1);
+		print_named_value(f, "TC_WB_ACTION_ENA", (ib[1] >> 15) & 0x1, 1);
+		print_named_value(f, "TCL1_ACTION_ENA", (ib[1] >> 16) & 0x1, 1);
+		print_named_value(f, "TC_ACTION_ENA", (ib[1] >> 17) & 0x1, 1);
+		print_named_value(f, "TC_NC_ACTION_ENA", (ib[1] >> 19) & 0x1, 1);
+		print_named_value(f, "TC_WC_ACTION_ENA", (ib[1] >> 20) & 0x1, 1);
+		print_named_value(f, "TC_MD_ACTION_ENA", (ib[1] >> 21) & 0x1, 1);
+		print_named_value(f, "DST_SEL", (ib[2] >> 16) & 0x3, 2);
+		print_named_value(f, "INT_SEL", (ib[2] >> 24) & 0x7, 3);
+		print_named_value(f, "DATA_SEL", ib[2] >> 29, 3);
+		print_named_value(f, "ADDRESS_LO", ib[3], 32);
+		print_named_value(f, "ADDRESS_HI", ib[4], 32);
+		print_named_value(f, "DATA_LO", ib[5], 32);
+		print_named_value(f, "DATA_HI", ib[6], 32);
+		print_named_value(f, "CTXID", ib[7], 32);
+		break;
+	case PKT3_WAIT_REG_MEM:
+		print_named_value(f, "OP", ib[1], 32);
+		print_named_value(f, "ADDRESS_LO", ib[2], 32);
+		print_named_value(f, "ADDRESS_HI", ib[3], 32);
+		print_named_value(f, "REF", ib[4], 32);
+		print_named_value(f, "MASK", ib[5], 32);
+		print_named_value(f, "POLL_INTERVAL", ib[6], 16);
+		break;
 	case PKT3_DRAW_INDEX_AUTO:
 		ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[1], ~0);
 		ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[2], ~0);
 		break;
 	case PKT3_DRAW_INDEX_2:
 		ac_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ib[1], ~0);
 		ac_dump_reg(f, R_0287E8_VGT_DMA_BASE, ib[2], ~0);
 		ac_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ib[3], ~0);
 		ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ib[4], ~0);
 		ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ib[5], ~0);
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index d329ad9..c69f4f6 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -273,20 +273,21 @@
 #define   R_500_DMA_DATA_WORD0		0x500 /* 0x[packet number][word index] */
 #define     S_500_CP_SYNC(x)		(((unsigned)(x) & 0x1) << 31)
 #define     S_500_SRC_SEL(x)		(((unsigned)(x) & 0x3) << 29)
 #define       V_500_SRC_ADDR		0
 #define       V_500_GDS			1 /* program SAS to 1 as well */
 #define       V_500_DATA		2
 #define       V_500_SRC_ADDR_TC_L2	3 /* new for CIK */
 #define     S_500_DSL_SEL(x)		(((unsigned)(x) & 0x3) << 20)
 #define       V_500_DST_ADDR		0
 #define       V_500_GDS			1 /* program DAS to 1 as well */
+#define       V_500_NOWHERE		2 /* new for GFX9 */
 #define       V_500_DST_ADDR_TC_L2	3 /* new for CIK */
 #define     S_500_ENGINE(x)		((x) & 0x1)
 #define       V_500_ME			0
 #define       V_500_PFP			1
 #define   R_501_SRC_ADDR_LO		0x501
 #define   R_502_SRC_ADDR_HI		0x502
 #define   R_503_DST_ADDR_LO		0x503
 #define   R_504_DST_ADDR_HI		0x504
 
 #define R_000E4C_SRBM_STATUS2                                           0x000E4C
-- 
2.7.4