[Mesa-dev] [PATCH 010/140] amdgpu/addrlib: add disableLinearOpt flag

[Marek Olšák]

From: Xavi Zhang <xavi.zhang at amd.com>

---
 src/amd/addrlib/addrinterface.h   | 3 ++-
 src/amd/addrlib/core/addrcommon.h | 3 ++-
 src/amd/addrlib/core/addrlib.cpp  | 5 ++++-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 764377a..c6c4684 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -439,21 +439,22 @@ typedef union _ADDR_SURFACE_FLAGS
         UINT_32 qbStereo        : 1; ///< Quad buffer stereo surface
         UINT_32 pow2Pad         : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
         UINT_32 interleaved     : 1; ///< Special flag for interleaved YUV surface padding
         UINT_32 tcCompatible    : 1; ///< Flag indicates surface needs to be shader readable
         UINT_32 dispTileType    : 1; ///< NI: force display Tiling for 128 bit shared resoruce
         UINT_32 dccCompatible   : 1; ///< VI: whether to support dcc fast clear
         UINT_32 czDispCompatible: 1; ///< SI+: CZ family has a HW bug needs special alignment.
                                      ///  This flag indicates we need to follow the alignment with
                                      ///  CZ families or other ASICs under PX configuration + CZ.
         UINT_32 nonSplit        : 1; ///< CI: depth texture should not be split
-        UINT_32 reserved        : 10; ///< Reserved bits
+        UINT_32 disableLinearOpt: 1; ///< Disable tile mode optimization to linear
+        UINT_32 reserved        : 9; ///< Reserved bits
     };
 
     UINT_32 value;
 } ADDR_SURFACE_FLAGS;
 
 /**
 ***************************************************************************************************
 *   ADDR_COMPUTE_SURFACE_INFO_INPUT
 *
 *   @brief
diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h
index 88cbad0..60b3d81 100644
--- a/src/amd/addrlib/core/addrcommon.h
+++ b/src/amd/addrlib/core/addrcommon.h
@@ -126,21 +126,22 @@ union ADDR_CONFIG_FLAGS
         UINT_32 optimalBankSwap        : 1;    ///< New bank tiling for RV770 only
         UINT_32 noCubeMipSlicesPad     : 1;    ///< Disables faces padding for cubemap mipmaps
         UINT_32 fillSizeFields         : 1;    ///< If clients fill size fields in all input and
                                                ///  output structure
         UINT_32 ignoreTileInfo         : 1;    ///< Don't use tile info structure
         UINT_32 useTileIndex           : 1;    ///< Make tileIndex field in input valid
         UINT_32 useCombinedSwizzle     : 1;    ///< Use combined swizzle
         UINT_32 checkLast2DLevel       : 1;    ///< Check the last 2D mip sub level
         UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
         UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
-        UINT_32 reserved               : 23;   ///< Reserved bits for future use
+        UINT_32 disableLinearOpt       : 1;    ///< Disallow tile modes to be optimized to linear
+        UINT_32 reserved               : 22;   ///< Reserved bits for future use
     };
 
     UINT_32 value;
 };
 
 ///////////////////////////////////////////////////////////////////////////////////////////////////
 // Platform specific debug break defines
 ///////////////////////////////////////////////////////////////////////////////////////////////////
 #if DEBUG
     #if defined(__GNUC__)
diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp
index 4804b0d..f1a9fcb 100644
--- a/src/amd/addrlib/core/addrlib.cpp
+++ b/src/amd/addrlib/core/addrlib.cpp
@@ -258,20 +258,21 @@ ADDR_E_RETURNCODE AddrLib::Create(
         BOOL_32 initValid;
 
         // Pass createFlags to configFlags first since these flags may be overwritten
         pLib->m_configFlags.noCubeMipSlicesPad  = pCreateIn->createFlags.noCubeMipSlicesPad;
         pLib->m_configFlags.fillSizeFields      = pCreateIn->createFlags.fillSizeFields;
         pLib->m_configFlags.useTileIndex        = pCreateIn->createFlags.useTileIndex;
         pLib->m_configFlags.useCombinedSwizzle  = pCreateIn->createFlags.useCombinedSwizzle;
         pLib->m_configFlags.checkLast2DLevel    = pCreateIn->createFlags.checkLast2DLevel;
         pLib->m_configFlags.useHtileSliceAlign  = pCreateIn->createFlags.useHtileSliceAlign;
         pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile;
+        pLib->m_configFlags.disableLinearOpt    = FALSE;
 
         pLib->SetAddrChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision);
 
         pLib->SetMinPitchAlignPixels(pCreateIn->minPitchAlignPixels);
 
         // Global parameters initialized and remaining configFlags bits are set as well
         initValid = pLib->HwlInitGlobalParams(pCreateIn);
 
         if (initValid)
         {
@@ -3547,21 +3548,23 @@ BOOL_32 AddrLib::OptimizeTileMode(
         (pIn->numSamples <= 1)              &&
         (pIn->flags.display == FALSE)       &&
         (IsPrtTileMode(tileMode) == FALSE)  &&
         (pIn->flags.prt == FALSE))
     {
         // Check if linear mode is optimal
         if ((pIn->height == 1) &&
             (IsLinear(tileMode) == FALSE) &&
             (AddrElemLib::IsBlockCompressed(pIn->format) == FALSE) &&
             (pIn->flags.depth == FALSE) &&
-            (pIn->flags.stencil == FALSE))
+            (pIn->flags.stencil == FALSE) &&
+            (m_configFlags.disableLinearOpt == FALSE) &&
+            (pIn->flags.disableLinearOpt == FALSE))
         {
             tileMode = ADDR_TM_LINEAR_ALIGNED;
         }
         else if (IsMacroTiled(tileMode))
         {
             if (HwlDegradeBaseLevel(pIn))
             {
                 tileMode = (thickness == 1) ? ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK;
             }
             else if (thickness > 1)
-- 
2.7.4