[Mesa-dev] [PATCH 008/140] amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding path
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:42:18 UTC 2017
From: Xavi Zhang <xavi.zhang at amd.com>
Kaveri (2-pipe) macro tiling mode table was initially set to all
4-aspect-ratio so the swizzling path did not work for it and then we
chose to pad the offset. We now discover the root cause is that if
ratio > 2, the swizzling path does not work. So we can safely use the
same path for Kaveri.
---
src/amd/addrlib/r800/ciaddrlib.cpp | 30 --------------------
src/amd/addrlib/r800/ciaddrlib.h | 2 --
src/amd/addrlib/r800/egbaddrlib.cpp | 56 ++++++++++++++++++++++++++-----------
src/amd/addrlib/r800/egbaddrlib.h | 7 +----
4 files changed, 41 insertions(+), 54 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 1024ff2..5e5110a 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1607,50 +1607,20 @@ VOID CiAddrLib::HwlComputeTileDataWidthAndHeightLinear(
numTiles = 4;
break;
}
*pMacroWidth = numTiles * MicroTileWidth;
*pMacroHeight = numTiles * MicroTileHeight;
}
/**
***************************************************************************************************
-* CiAddrLib::HwlStereoCheckRightOffsetPadding
-*
-* @brief
-* check if the height needs extra padding for stereo right eye offset, to avoid swizzling
-*
-* @return
-* TRUE is the extra padding is needed
-*
-* @note
-* Kalindi (Kabini) is the only one that needs this padding as there is a uncertain
-* possible HW issue where the right eye displays incorrectly with some type of swizzles, if
-* the right eye offset is not 64KB aligned - EPR#366461
-* Other Kaveri APUs also need the padding according to DXX team's report otherwise
-* corruption observed. - EPR#374788
-***************************************************************************************************
-*/
-BOOL_32 CiAddrLib::HwlStereoCheckRightOffsetPadding() const
-{
- BOOL_32 bNeedPadding = FALSE;
-
- if (m_settings.isKaveri)
- {
- bNeedPadding = TRUE;
- }
-
- return bNeedPadding;
-}
-
-/**
-***************************************************************************************************
* CiAddrLib::HwlComputeMetadataNibbleAddress
*
* @brief
* calculate meta data address based on input information
*
* ¶meter
* uncompressedDataByteAddress - address of a pixel in color surface
* dataBaseByteAddress - base address of color surface
* metadataBaseByteAddress - base address of meta ram
* metadataBitSize - meta key size, 8 for DCC, 4 for cmask
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 05e9eda..4862bab 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -139,22 +139,20 @@ protected:
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual BOOL_32 HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
AddrTileMode* pTileMode,
AddrTileType* pTileType) const;
- virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const;
-
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
protected:
virtual VOID HwlPadDimensions(
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 5d80906..2085dc5 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -518,38 +518,28 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
pIn->flags,
numSamples,
pOut->pTileInfo,
padDims,
pIn->mipLevel,
&paddedPitch, pOut->pitchAlign,
&paddedHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
if (pIn->flags.qbStereo &&
- (pOut->pStereoInfo != NULL) &&
- HwlStereoCheckRightOffsetPadding())
+ (pOut->pStereoInfo != NULL))
{
- // Eye height's bank bits are different from y == 0?
- // Since 3D rendering treats right eye buffer starting from y == "eye height" while
- // display engine treats it to be 0, so the bank bits may be different, we pad
- // more in height to make sure y == "eye height" has the same bank bits as y == 0.
- UINT_32 checkMask = pOut->pTileInfo->banks - 1;
- UINT_32 bankBits = 0;
- do
- {
- bankBits = (paddedHeight / 8 / pOut->pTileInfo->bankHeight) & checkMask;
+ UINT_32 stereoHeightAlign = HwlStereoCheckRightOffsetPadding(pOut->pTileInfo);
- if (bankBits)
- {
- paddedHeight += pOut->heightAlign;
- }
- } while (bankBits);
+ if (stereoHeightAlign != 0)
+ {
+ paddedHeight = PowTwoAlign(paddedHeight, stereoHeightAlign);
+ }
}
//
// Compute the size of a slice.
//
bytesPerSlice = BITS_TO_BYTES(static_cast<UINT_64>(paddedPitch) *
paddedHeight * NextPow2(pIn->bpp) * numSamples);
pOut->pitch = paddedPitch;
// Put this check right here to workaround special mipmap cases which the original height
@@ -4584,10 +4574,44 @@ UINT_64 EgBasedAddrLib::HwlGetSizeAdjustmentMicroTiled(
physicalSliceSize = logicalSliceSize * thickness;
//
// R800 will always pad physical slice size to baseAlign which is pipe_interleave_bytes
//
ADDR_ASSERT((physicalSliceSize % baseAlign) == 0)
return logicalSliceSize;
}
+/**
+***************************************************************************************************
+* EgBasedAddrLib::HwlStereoCheckRightOffsetPadding
+*
+* @brief
+* check if the height needs extra padding for stereo right eye offset, to avoid swizzling
+*
+* @return
+* TRUE is the extra padding is needed
+*
+***************************************************************************************************
+*/
+UINT_32 EgBasedAddrLib::HwlStereoCheckRightOffsetPadding(
+ ADDR_TILEINFO* pTileInfo ///< Tiling info
+ ) const
+{
+ UINT_32 stereoHeightAlign = 0;
+
+ if (pTileInfo->macroAspectRatio > 2)
+ {
+ // Since 3D rendering treats right eye surface starting from y == "eye height" while
+ // display engine treats it to be 0, so the bank bits may be different.
+ // Additional padding in height is required to make sure it's possible
+ // to achieve synonym by adjusting bank swizzle of right eye surface.
+
+ static const UINT_32 StereoAspectRatio = 2;
+ stereoHeightAlign = pTileInfo->banks *
+ pTileInfo->bankHeight *
+ MicroTileHeight /
+ StereoAspectRatio;
+ }
+
+ return stereoHeightAlign;
+}
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index 25e3896..ca1d07d 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -217,26 +217,21 @@ protected:
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const
{
}
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const
{
}
- /// Virtual function to check if the height needs extra padding
- /// for stereo right eye offset, to avoid bank pipe swizzle
- virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const
- {
- return FALSE;
- }
+ virtual UINT_32 HwlStereoCheckRightOffsetPadding(ADDR_TILEINFO* pTileInfo) const;
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const;
// Protected non-virtual functions
/// Mip level functions
AddrTileMode ComputeSurfaceMipLevelTileMode(
--
2.7.4
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