[Mesa-dev] [PATCH 040/140] amdgpu/addrlib: Add flag to report if a surface can have dcc ram

[Marek Olšák]

From: Frans Gu <frans.gu at amd.com>

---
 src/amd/addrlib/addrinterface.h    |  3 ++-
 src/amd/addrlib/r800/ciaddrlib.cpp | 25 ++++++++++++++++++++++++-
 src/amd/addrlib/r800/siaddrlib.h   |  4 ++--
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 55f3ebc..a2a36cd 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -602,21 +602,22 @@ typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
     INT_32          tileIndex;      ///< Tile index, MAY be "downgraded"
 
     INT_32          macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
     /// Output flags
     struct
     {
         /// Special information to work around SI mipmap swizzle bug UBTS #317508
         UINT_32     last2DLevel  : 1;  ///< TRUE if this is the last 2D(3D) tiled
                                        ///< Only meaningful when create flag checkLast2DLevel is set
         UINT_32     tcCompatible : 1;  ///< If the surface can be shader compatible
-        UINT_32     reserved     :30;  ///< Reserved bits
+        UINT_32     dccUnsupport : 1;  ///< If the surface can support DCC compressed rendering
+        UINT_32     reserved     :29;  ///< Reserved bits
     };
 
     UINT_32         equationIndex;     ///< Equation index in the equation table;
 
     UINT_32         blockWidth;        ///< Width in element inside one block(1D->Micro, 2D->Macro)
     UINT_32         blockHeight;       ///< Height in element inside one block(1D->Micro, 2D->Macro)
     UINT_32         blockSlices;       ///< Slice number inside one block(1D->Micro, 2D->Macro)
 
     /// Stereo info
     ADDR_QBSTEREOINFO*  pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index e5dfea2..ed7958d 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1377,36 +1377,59 @@ VOID CiLib::HwlSetupTileInfo(
                     // Switching to next tile mode entry to make sure macro tile size is 64KB
                     index += 1;
 
                     tileInfo.pipeConfig = m_tileTable[index].info.pipeConfig;
 
                     macroTileBytes = (bpp >> 3) * 64 * numSamples * thickness *
                                      HwlGetPipes(&tileInfo) * tileInfo.banks *
                                      tileInfo.bankWidth * tileInfo.bankHeight;
 
                     ADDR_ASSERT(macroTileBytes == PrtTileBytes);
+
+                    pOut->tcCompatible = FALSE;
+                    pOut->dccUnsupport = TRUE;
                 }
             }
         }
     }
     else
     {
         // A pre-filled tile info is ready
         index = pOut->tileIndex;
         macroModeIndex = pOut->macroModeIndex;
 
         // pass tile type back for post tile index compute
         pOut->tileType = inTileType;
+
+        if (flags.depth || flags.stencil)
+        {
+            // tileSize = thickness * bpp * numSamples * 8 * 8 / 8
+            UINT_32 tileSize = thickness * bpp * numSamples * 8;
+
+            // Turn off tc compatible if row_size is smaller than tile size (tile split occurs).
+            if (m_rowSize < tileSize)
+            {
+                flags.tcCompatible = FALSE;
+                pOut->tcCompatible = FALSE;
+            }
+        }
+
+        UINT_32 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
+
+        if (m_pipes != numPipes)
+        {
+            pOut->dccUnsupport = TRUE;
+        }
     }
 
     // We only need to set up tile info if there is a valid index but macroModeIndex is invalid
-    if (index != TileIndexInvalid && macroModeIndex == TileIndexInvalid)
+    if ((index != TileIndexInvalid) && (macroModeIndex == TileIndexInvalid))
     {
         macroModeIndex = HwlComputeMacroModeIndex(index, flags, bpp, numSamples, pTileInfo);
 
         // Copy to pOut->tileType/tileIndex/macroModeIndex
         pOut->tileIndex = index;
         pOut->tileType = m_tileTable[index].type; // Or inTileType, the samea
         pOut->macroModeIndex = macroModeIndex;
     }
     else if (tileMode == ADDR_TM_LINEAR_GENERAL)
     {
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index c40b546..80c5cf4 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -270,42 +270,42 @@ protected:
 
     BOOL_32 DecodeGbRegs(
         const ADDR_REGISTER_VALUE* pRegValue);
 
     const TileConfig* GetTileSetting(
         UINT_32 index) const;
 
     // Initialize equation table
     VOID InitEquationTable();
 
+    UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
+
     static const UINT_32    TileTableSize = 32;
     TileConfig          m_tileTable[TileTableSize];
     UINT_32                 m_noOfEntries;
 
     // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
     static const UINT_32    MaxNumElementBytes  = 5;
     // More than half slots in tile mode table can't support equation
     static const UINT_32    EquationTableSize = (MaxNumElementBytes * TileTableSize) / 2;
     // Equation table
     ADDR_EQUATION           m_equationTable[EquationTableSize];
     UINT_32                 m_blockWidth[EquationTableSize];
     UINT_32                 m_blockHeight[EquationTableSize];
     UINT_32                 m_blockSlices[EquationTableSize];
     // Number of equation entries in the table
     UINT_32                 m_numEquations;
     // Equation lookup table according to bpp and tile index
     UINT_32                 m_equationLookupTable[MaxNumElementBytes][TileTableSize];
 
 private:
 
-    UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
-
     VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
     BOOL_32 InitTileSettingTable(const UINT_32 *pSetting, UINT_32 noOfEntries);
 
     SIChipSettings          m_settings;
 };
 
 } // V1
 } // Addr
 
 #endif
-- 
2.7.4