[Mesa-dev] [PATCH 076/140] radeonsi/gfx9: CP DMA changes
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:43:26 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/amd/common/sid.h | 1 +
src/gallium/drivers/radeonsi/si_cp_dma.c | 37 ++++++++++++++++++++++++++------
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index e0c3a02..75ba965 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -217,20 +217,21 @@
#define V_411_SRC_ADDR 0
#define V_411_GDS 1 /* program SAS to 1 as well */
#define V_411_DATA 2
#define V_411_SRC_ADDR_TC_L2 3 /* new for CIK */
#define S_411_ENGINE(x) (((unsigned)(x) & 0x1) << 27)
#define V_411_ME 0
#define V_411_PFP 1
#define S_411_DSL_SEL(x) (((unsigned)(x) & 0x3) << 20)
#define V_411_DST_ADDR 0
#define V_411_GDS 1 /* program DAS to 1 as well */
+#define V_411_NOWHERE 2 /* new for GFX9 */
#define V_411_DST_ADDR_TC_L2 3 /* new for CIK */
#define S_411_SRC_ADDR_HI(x) ((x) & 0xffff)
#define R_412_CP_DMA_WORD2 0x412 /* 0x[packet number][word index] */
#define S_412_DST_ADDR_LO(x) ((x) & 0xffffffff)
#define R_413_CP_DMA_WORD3 0x413 /* 0x[packet number][word index] */
#define S_413_DST_ADDR_HI(x) ((x) & 0xffff)
#define R_414_COMMAND 0x414
#define S_414_BYTE_COUNT_GFX6(x) ((x) & 0x1fffff)
#define S_414_BYTE_COUNT_GFX9(x) ((x) & 0x3ffffff)
#define S_414_DISABLE_WR_CONFIRM_GFX6(x) (((unsigned)(x) & 0x1) << 21) /* not on GFX9 */
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index a564468..ccc8672 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -35,45 +35,68 @@
* It should be set on the last CP DMA packet. */
#define CP_DMA_SYNC (1 << 0)
/* Set this if the source data was used as a destination in a previous CP DMA
* packet. It's for preventing a read-after-write (RAW) hazard between two
* CP DMA packets. */
#define CP_DMA_RAW_WAIT (1 << 1)
#define CP_DMA_USE_L2 (1 << 2) /* CIK+ */
#define CP_DMA_CLEAR (1 << 3)
+/* The max number of bytes that can be copied per packet. */
+static inline unsigned cp_dma_max_byte_count(struct si_context *sctx)
+{
+ unsigned max = sctx->b.chip_class >= GFX9 ?
+ S_414_BYTE_COUNT_GFX9(~0u) :
+ S_414_BYTE_COUNT_GFX6(~0u);
+
+ /* make it aligned for optimal performance */
+ return max & ~(SI_CPDMA_ALIGNMENT - 1);
+}
+
+
/* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
* a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
* clear value.
*/
static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
uint64_t src_va, unsigned size, unsigned flags,
enum r600_coherency coher)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- uint32_t header = 0, command = S_414_BYTE_COUNT_GFX6(size);
+ uint32_t header = 0, command = 0;
assert(size);
- assert(size <= CP_DMA_MAX_BYTE_COUNT);
+ assert(size <= cp_dma_max_byte_count(sctx));
+
+ if (sctx->b.chip_class >= GFX9)
+ command |= S_414_BYTE_COUNT_GFX9(size);
+ else
+ command |= S_414_BYTE_COUNT_GFX6(size);
/* Sync flags. */
if (flags & CP_DMA_SYNC)
header |= S_411_CP_SYNC(1);
- else
- command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
+ else {
+ if (sctx->b.chip_class >= GFX9)
+ command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
+ else
+ command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
+ }
if (flags & CP_DMA_RAW_WAIT)
command |= S_414_RAW_WAIT(1);
/* Src and dst flags. */
- if (flags & CP_DMA_USE_L2)
+ if (sctx->b.chip_class >= GFX9 && src_va == dst_va)
+ header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
+ else if (flags & CP_DMA_USE_L2)
header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
if (flags & CP_DMA_CLEAR)
header |= S_411_SRC_SEL(V_411_DATA);
else if (flags & CP_DMA_USE_L2)
header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
if (sctx->b.chip_class >= CIK) {
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
radeon_emit(cs, header);
@@ -226,21 +249,21 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
return;
}
uint64_t va = rdst->gpu_address + offset;
/* Flush the caches. */
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
while (size) {
- unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
+ unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
unsigned dma_flags = tc_l2_flag | CP_DMA_CLEAR;
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0,
&is_first, &dma_flags);
/* Emit the clear packet. */
si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
size -= byte_count;
va += byte_count;
@@ -352,21 +375,21 @@ void si_copy_buffer(struct si_context *sctx,
if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC))
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
/* This is the main part doing the copying. Src is always aligned. */
main_dst_offset = dst_offset + skipped_size;
main_src_offset = src_offset + skipped_size;
while (size) {
unsigned dma_flags = tc_l2_flag;
- unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
+ unsigned byte_count = MIN2(size, cp_dma_max_byte_count(sctx));
si_cp_dma_prepare(sctx, dst, src, byte_count,
size + skipped_size + realign_size,
user_flags, &is_first, &dma_flags);
si_emit_cp_dma(sctx, main_dst_offset, main_src_offset,
byte_count, dma_flags, R600_COHERENCY_SHADER);
size -= byte_count;
main_src_offset += byte_count;
--
2.7.4
More information about the mesa-dev
mailing list