[Mesa-dev] [PATCH 075/140] radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_query.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index e269c39..dcd217b 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -644,40 +644,40 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
 					uint64_t va)
 {
 	struct radeon_winsys_cs *cs = ctx->gfx.cs;
 
 	switch (query->b.type) {
 	case PIPE_QUERY_OCCLUSION_COUNTER:
 	case PIPE_QUERY_OCCLUSION_PREDICATE:
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 		break;
 	case PIPE_QUERY_PRIMITIVES_EMITTED:
 	case PIPE_QUERY_PRIMITIVES_GENERATED:
 	case PIPE_QUERY_SO_STATISTICS:
 	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 		break;
 	case PIPE_QUERY_TIME_ELAPSED:
 		r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
 					 0, 3, NULL, va, 0, 0);
 		break;
 	case PIPE_QUERY_PIPELINE_STATISTICS:
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 		break;
 	default:
 		assert(0);
 	}
 	r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
 			RADEON_PRIO_QUERY);
 }
 
 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
 				     struct r600_query_hw *query)
@@ -720,50 +720,50 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
 	struct radeon_winsys_cs *cs = ctx->gfx.cs;
 	uint64_t fence_va = 0;
 
 	switch (query->b.type) {
 	case PIPE_QUERY_OCCLUSION_COUNTER:
 	case PIPE_QUERY_OCCLUSION_PREDICATE:
 		va += 8;
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 
 		fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
 		break;
 	case PIPE_QUERY_PRIMITIVES_EMITTED:
 	case PIPE_QUERY_PRIMITIVES_GENERATED:
 	case PIPE_QUERY_SO_STATISTICS:
 	case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
 		va += query->result_size/2;
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 		break;
 	case PIPE_QUERY_TIME_ELAPSED:
 		va += 8;
 		/* fall through */
 	case PIPE_QUERY_TIMESTAMP:
 		r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
 					 0, 3, NULL, va, 0, 0);
 		fence_va = va + 8;
 		break;
 	case PIPE_QUERY_PIPELINE_STATISTICS: {
 		unsigned sample_size = (query->result_size - 8) / 2;
 
 		va += sample_size;
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
 		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
 		radeon_emit(cs, va);
-		radeon_emit(cs, (va >> 32) & 0xFFFF);
+		radeon_emit(cs, va >> 32);
 
 		fence_va = va + sample_size;
 		break;
 	}
 	default:
 		assert(0);
 	}
 	r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
 			RADEON_PRIO_QUERY);
 
@@ -834,26 +834,35 @@ static void r600_emit_query_predication(struct r600_common_context *ctx,
 	if (ctx->render_cond_invert)
 		op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
 	else
 		op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
 
 	op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
 	
 	/* emit predicate packets for all data blocks */
 	for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
 		unsigned results_base = 0;
-		uint64_t va = qbuf->buf->gpu_address;
+		uint64_t va_base = qbuf->buf->gpu_address;
 
 		while (results_base < qbuf->results_end) {
-			radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
-			radeon_emit(cs, va + results_base);
-			radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
+			uint64_t va = va_base + results_base;
+
+			if (ctx->chip_class >= GFX9) {
+				radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
+				radeon_emit(cs, op);
+				radeon_emit(cs, va);
+				radeon_emit(cs, va >> 32);
+			} else {
+				radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
+				radeon_emit(cs, va);
+				radeon_emit(cs, op | ((va >> 32) & 0xFF));
+			}
 			r600_emit_reloc(ctx, &ctx->gfx, qbuf->buf, RADEON_USAGE_READ,
 					RADEON_PRIO_QUERY);
 			results_base += query->result_size;
 
 			/* set CONTINUE bit for all packets except the first */
 			op |= PREDICATION_CONTINUE;
 		}
 	}
 }
 
-- 
2.7.4