[Mesa-dev] [PATCH 090/140] radeonsi/gfx9: draw changes
Marek Olšák
maraeo at gmail.com
Mon Mar 20 22:43:40 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_state_draw.c | 43 ++++++++++++++++++++--------
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8c6e9cd..f01ac01 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -20,20 +20,21 @@
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Christian König <christian.koenig at amd.com>
*/
#include "si_pipe.h"
#include "radeon/r600_cs.h"
#include "sid.h"
+#include "gfx9d.h"
#include "util/u_index_modify.h"
#include "util/u_upload_mgr.h"
#include "util/u_prim.h"
#include "ac_debug.h"
static unsigned si_conv_pipe_prim(unsigned mode)
{
static const unsigned prim_conv[] = {
@@ -372,21 +373,23 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
/* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
if (ia_switch_on_eoi)
partial_es_wave = true;
return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
- max_primgroup_in_wave : 0);
+ max_primgroup_in_wave : 0) |
+ S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
+ S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
}
void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
{
for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
for (int multi_instances = 0; multi_instances < 2; multi_instances++)
for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
for (int count_from_so = 0; count_from_so < 2; count_from_so++)
for (int line_stipple = 0; line_stipple < 2; line_stipple++)
@@ -499,21 +502,23 @@ static void si_emit_draw_registers(struct si_context *sctx,
unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
unsigned ia_multi_vgt_param, num_patches = 0;
if (sctx->tes_shader.cso)
si_emit_derived_tess_state(sctx, info, &num_patches);
ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
/* Draw state. */
if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
- if (sctx->b.chip_class >= CIK)
+ if (sctx->b.chip_class >= GFX9)
+ radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
+ else if (sctx->b.chip_class >= CIK)
radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
else
radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
sctx->last_multi_vgt_param = ia_multi_vgt_param;
}
if (prim != sctx->last_prim) {
if (sctx->b.chip_class >= CIK)
radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
else
@@ -522,21 +527,27 @@ static void si_emit_draw_registers(struct si_context *sctx,
sctx->last_prim = prim;
}
if (gs_out_prim != sctx->last_gs_out_prim) {
radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
sctx->last_gs_out_prim = gs_out_prim;
}
/* Primitive restart. */
if (info->primitive_restart != sctx->last_primitive_restart_en) {
- radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
+ if (sctx->b.chip_class >= GFX9)
+ radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
+ info->primitive_restart);
+ else
+ radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
+ info->primitive_restart);
+
sctx->last_primitive_restart_en = info->primitive_restart;
}
if (info->primitive_restart &&
(info->restart_index != sctx->last_restart_index ||
sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
info->restart_index);
sctx->last_restart_index = info->restart_index;
}
@@ -571,42 +582,50 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, 0); /* unused */
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
t->buf_filled_size, RADEON_USAGE_READ,
RADEON_PRIO_SO_FILLED_SIZE);
}
/* draw packet */
if (info->indexed) {
if (ib->index_size != sctx->last_index_size) {
- radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
+ unsigned index_type;
/* index type */
switch (ib->index_size) {
case 1:
- radeon_emit(cs, V_028A7C_VGT_INDEX_8);
+ index_type = V_028A7C_VGT_INDEX_8;
break;
case 2:
- radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
- (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
- V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
+ index_type = V_028A7C_VGT_INDEX_16 |
+ (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
+ V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
break;
case 4:
- radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
- (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
- V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
+ index_type = V_028A7C_VGT_INDEX_32 |
+ (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
+ V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
break;
default:
assert(!"unreachable");
return;
}
+ if (sctx->b.chip_class >= GFX9) {
+ radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
+ 2, index_type);
+ } else {
+ radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
+ radeon_emit(cs, index_type);
+ }
+
sctx->last_index_size = ib->index_size;
}
index_max_size = (ib->buffer->width0 - ib->offset) /
ib->index_size;
index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource *)ib->buffer,
RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
@@ -711,21 +730,21 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, info->indirect_stride);
radeon_emit(cs, di_src_sel);
}
} else {
if (info->indexed) {
index_va += info->start * ib->index_size;
radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
radeon_emit(cs, index_max_size);
radeon_emit(cs, index_va);
- radeon_emit(cs, (index_va >> 32UL) & 0xFF);
+ radeon_emit(cs, index_va >> 32);
radeon_emit(cs, info->count);
radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
} else {
radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
radeon_emit(cs, info->count);
radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
}
}
}
--
2.7.4
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