[Mesa-dev] [PATCH] radv: set base/ranges for push constant loads.

[Dave Airlie]

On 5 May 2017 at 10:43, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> This isn't necessary yet but I'd like to use the range in
> some future patches.
>
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/amd/vulkan/radv_meta_blit2d.c     |  2 ++
>  src/amd/vulkan/radv_meta_buffer.c     |  2 ++
>  src/amd/vulkan/radv_meta_bufimage.c   | 14 ++++++++++++++
>  src/amd/vulkan/radv_meta_resolve_cs.c |  4 ++++
>  src/amd/vulkan/radv_query.c           |  2 ++
>  5 files changed, 24 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
> index 10e20d2..ae759af 100644
> --- a/src/amd/vulkan/radv_meta_blit2d.c
> +++ b/src/amd/vulkan/radv_meta_blit2d.c
> @@ -488,6 +488,8 @@ build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
>         sampler->data.binding = 0;
>
>         nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(width, 0);
> +       nir_intrinsic_set_range(width, 4);
>         width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
>         width->num_components = 1;
>         nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
> diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
> index 0bb926f..68de81e 100644
> --- a/src/amd/vulkan/radv_meta_buffer.c
> +++ b/src/amd/vulkan/radv_meta_buffer.c
> @@ -36,6 +36,8 @@ build_buffer_fill_shader(struct radv_device *dev)
>         nir_builder_instr_insert(&b, &dst_buf->instr);
>
>         nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(load, 0);
> +       nir_intrinsic_set_range(load, 4);
>         load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         load->num_components = 1;
>         nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, "fill_value");
> diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c
> index 1d491ac..a40d4b4 100644
> --- a/src/amd/vulkan/radv_meta_bufimage.c
> +++ b/src/amd/vulkan/radv_meta_bufimage.c
> @@ -68,12 +68,16 @@ build_nir_itob_compute_shader(struct radv_device *dev)
>
>
>         nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(offset, 0);
> +       nir_intrinsic_set_range(offset, 12);
>         offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         offset->num_components = 2;
>         nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset");
>         nir_builder_instr_insert(&b, &offset->instr);
>
>         nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(stride, 0);
> +       nir_intrinsic_set_range(stride, 12);
>         stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
>         stride->num_components = 1;
>         nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
> @@ -264,12 +268,16 @@ build_nir_btoi_compute_shader(struct radv_device *dev)
>         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
>
>         nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(offset, 0);
> +       nir_intrinsic_set_range(offset, 12);
>         offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         offset->num_components = 2;
>         nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset");
>         nir_builder_instr_insert(&b, &offset->instr);
>
>         nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(stride, 0);
> +       nir_intrinsic_set_range(stride, 12);
>         stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
>         stride->num_components = 1;
>         nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
> @@ -460,12 +468,16 @@ build_nir_itoi_compute_shader(struct radv_device *dev)
>         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
>
>         nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(src_offset, 0);
> +       nir_intrinsic_set_range(src_offset, 16);
>         src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         src_offset->num_components = 2;
>         nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
>         nir_builder_instr_insert(&b, &src_offset->instr);
>
>         nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(dst_offset, 0);
> +       nir_intrinsic_set_range(dst_offset, 16);
>         dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
>         dst_offset->num_components = 2;
>         nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
> @@ -642,6 +654,8 @@ build_nir_cleari_compute_shader(struct radv_device *dev)
>         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
>
>         nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(clear_val, 0);
> +       nir_intrinsic_set_range(clear_val, 16);
>         clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         clear_val->num_components = 4;
>         nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value");
> diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
> index dc4a1bb..56523b8 100644
> --- a/src/amd/vulkan/radv_meta_resolve_cs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_cs.c
> @@ -71,12 +71,16 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, int sampl
>         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
>
>         nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(src_offset, 0);
> +       nir_intrinsic_set_range(src_offset, 16);
>         src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
>         src_offset->num_components = 2;
>         nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
>         nir_builder_instr_insert(&b, &src_offset->instr);
>
>         nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +       nir_intrinsic_set_base(src_offset, 0);
> +       nir_intrinsic_set_range(src_offset, 16);

Oops one bug here, noticed it myself.

Dave.