[Mesa-dev] [PATCH 11/11] radeonsi: dump compute descriptor lists

[Marek Olšák]

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On May 8, 2017 5:39 PM, "Nicolai Hähnle" <nhaehnle at gmail.com> wrote:

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/gallium/drivers/radeonsi/si_debug.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/
radeonsi/si_debug.c
index d39b303..d08a8fc 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -490,20 +490,29 @@ static void si_dump_descriptors(struct si_context
*sctx,
 static void si_dump_gfx_descriptors(struct si_context *sctx,
                                    const struct si_shader_ctx_state *state,
                                    FILE *f)
 {
        if (!state->cso || !state->current)
                return;

        si_dump_descriptors(sctx, state->cso->type, &state->cso->info, f);
 }

+static void si_dump_compute_descriptors(struct si_context *sctx, FILE *f)
+{
+       if (!sctx->cs_shader_state.program ||
+           sctx->cs_shader_state.program != sctx->cs_shader_state.emitted_
program)
+               return;
+
+       si_dump_descriptors(sctx, PIPE_SHADER_COMPUTE, NULL, f);
+}
+
 struct si_shader_inst {
        char text[160];  /* one disasm line */
        unsigned offset; /* instruction offset */
        unsigned size;   /* instruction size = 4 or 8 */
 };

 /* Split a disassembly string into lines and add them to the array pointed
  * to by "instructions". */
 static void si_add_split_disasm(const char *disasm,
                                uint64_t start_addr,
@@ -793,20 +802,21 @@ static void si_dump_debug_state(struct pipe_context
*ctx, FILE *f,
                        si_dump_command("Wave information", "umr -O bits
-wa", f);
                }

                si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_
BUFFERS],
                                        "", "RW buffers",
SI_NUM_RW_BUFFERS, f);
                si_dump_gfx_descriptors(sctx, &sctx->vs_shader, f);
                si_dump_gfx_descriptors(sctx, &sctx->tcs_shader, f);
                si_dump_gfx_descriptors(sctx, &sctx->tes_shader, f);
                si_dump_gfx_descriptors(sctx, &sctx->gs_shader, f);
                si_dump_gfx_descriptors(sctx, &sctx->ps_shader, f);
+               si_dump_compute_descriptors(sctx, f);
        }

        if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
                si_dump_bo_list(sctx, &sctx->last_gfx, f);
                si_dump_last_ib(sctx, f);

                fprintf(f, "Done.\n");

                /* dump only once */
                radeon_clear_saved_cs(&sctx->last_gfx);
--
2.9.3

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