[Mesa-dev] [PATCH 2/3] i965: Change GEN_GEN < 7 to GEN_GEN == 6 in 3DSTATE_VS code.

[Kenneth Graunke]

This whole code is surrounded in #if GEN_GEN >= 6, and this code only
applies on Sandybridge.  So, use GEN_GEN == 6 to reduce the delta in
the next patch, when we add Gen4-5 support.
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index cf53c00e1b7..4c6cb1a9b71 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1728,25 +1728,24 @@ genX(upload_vs_state)(struct brw_context *brw)
       brw_vue_prog_data(brw->vs.base.prog_data);
    const struct brw_stage_prog_data *stage_prog_data = &vue_prog_data->base;
 
    assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
           vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
 
+#if GEN_GEN == 6
    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
     *
     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
     *   command that causes the VS Function Enable to toggle. Pipeline
     *   flush can be executed by sending a PIPE_CONTROL command with CS
     *   stall bit set and a post sync operation.
     *
     * We've already done such a flush at the start of state upload, so we
     * don't need to do another one here.
     */
-
-#if GEN_GEN < 7
    brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), cvs) {
       if (stage_state->push_const_size != 0) {
          cvs.Buffer0Valid = true;
          cvs.PointertoVSConstantBuffer0 = stage_state->push_const_offset;
          cvs.VSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
       }
@@ -1767,13 +1766,13 @@ genX(upload_vs_state)(struct brw_context *brw)
 
       vs.UserClipDistanceCullTestEnableBitmask =
          vue_prog_data->cull_distance_mask;
 #endif
    }
 
-#if GEN_GEN < 7
+#if GEN_GEN == 6
    /* Based on my reading of the simulator, the VS constants don't get
     * pulled into the VS FF unit until an appropriate pipeline flush
     * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
     * references to them into a little FIFO.  The flushes are common,
     * but don't reliably happen between this and a 3DPRIMITIVE, causing
     * the primitive to use the wrong constants.  Then the FIFO
@@ -1794,18 +1793,18 @@ genX(upload_vs_state)(struct brw_context *brw)
                                PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 #endif
 }
 
 static const struct brw_tracked_state genX(vs_state) = {
    .dirty = {
-      .mesa  = (GEN_GEN < 7 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0),
+      .mesa  = (GEN_GEN == 6 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0),
       .brw   = BRW_NEW_BATCH |
                BRW_NEW_BLORP |
                BRW_NEW_CONTEXT |
                BRW_NEW_VS_PROG_DATA |
-               (GEN_GEN < 7 ? BRW_NEW_VERTEX_PROGRAM : 0),
+               (GEN_GEN == 6 ? BRW_NEW_VERTEX_PROGRAM : 0),
    },
    .emit = genX(upload_vs_state),
 };
 #endif
 
 /* ---------------------------------------------------------------------- */
-- 
2.12.2