[Mesa-dev] [PATCH 2/4] genxml: Increase the field length by 1 bit.
Rafael Antognolli
rafael.antognolli at intel.com
Fri May 19 16:02:44 UTC 2017
VS, HS, DS and GS URB Starting Address field on the respective
3DSTATE_URB_?S instructions is 5 bits on gen7. However, if VS is the
only step enabled, the whole URB gets allocated (except for push
constant space) for the VS. But on some configurations, the size of the
URB is 32 "chunks" (8kB each chunk), so the starting address for all the
other shaders would be 32. But the field does not allow that (5 bits
means the max value is 31), and if we are using genxml, it will enforce
that we don't go over this size.
Unfortunately, the current code makes use of 6 bits (bits 30:25 and bit
31), by setting that to 32, so the 1 bit that is said on the
documentation to be MBZ is actually set to 1. But it works fine with
that.
I tried setting that address field to 0 when those shaders are not
active, while keeping the MBZ bit (31) at zero too, but that causes GPU
hangs. So my guess here is that the documentation is wrong and that this
field is actually 6 bits long, instead of 5.
Additionally, the same happens on Haswell, with these fields being 7
bits long instead of 6.
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
---
src/intel/genxml/gen7.xml | 20 ++++++++++++++++----
src/intel/genxml/gen75.xml | 20 ++++++++++++++++----
2 files changed, 32 insertions(+), 8 deletions(-)
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index c98327a..ed5d593 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1748,7 +1748,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="50"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="DS URB Starting Address" start="57" end="61" type="uint"/>
+ <!-- The docs say that this field is 5 bits long, but tests have shown
+ that it is actually 6, and we do need the 6 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="DS URB Starting Address" start="57" end="62" type="uint"/>
<field name="DS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="DS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -1759,7 +1762,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="51"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="GS URB Starting Address" start="57" end="61" type="uint"/>
+ <!-- The docs say that this field is 5 bits long, but tests have shown
+ that it is actually 6, and we do need the 6 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="GS URB Starting Address" start="57" end="62" type="uint"/>
<field name="GS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="GS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -1770,7 +1776,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="49"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="HS URB Starting Address" start="57" end="61" type="uint"/>
+ <!-- The docs say that this field is 5 bits long, but tests have shown
+ that it is actually 6, and we do need the 6 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="HS URB Starting Address" start="57" end="62" type="uint"/>
<field name="HS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="HS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -1781,7 +1790,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="48"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="VS URB Starting Address" start="57" end="61" type="uint"/>
+ <!-- The docs say that this field is 5 bits long, but tests have shown
+ that it is actually 6, and we do need the 6 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="VS URB Starting Address" start="57" end="62" type="uint"/>
<field name="VS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="VS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 11f1462..36f0a0b 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2061,7 +2061,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="50"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="DS URB Starting Address" start="57" end="62" type="uint"/>
+ <!-- The docs say that this field is 6 bits long, but tests have shown
+ that it is actually 6, and we do need the 7 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="DS URB Starting Address" start="57" end="63" type="uint"/>
<field name="DS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="DS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -2072,8 +2075,11 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="51"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="GS URB Starting Address" start="57" end="62" type="uint"/>
+ <field name="GS URB Starting Address" start="57" end="63" type="uint"/>
<field name="GS URB Entry Allocation Size" start="48" end="56" type="uint"/>
+ <!-- The docs say that this field is 6 bits long, but tests have shown
+ that it is actually 6, and we do need the 7 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
<field name="GS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -2083,7 +2089,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="49"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="HS URB Starting Address" start="57" end="62" type="uint"/>
+ <!-- The docs say that this field is 6 bits long, but tests have shown
+ that it is actually 6, and we do need the 7 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="HS URB Starting Address" start="57" end="63" type="uint"/>
<field name="HS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="HS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
@@ -2094,7 +2103,10 @@
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="48"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
- <field name="VS URB Starting Address" start="57" end="62" type="uint"/>
+ <!-- The docs say that this field is 6 bits long, but tests have shown
+ that it is actually 6, and we do need the 7 bits to inform that the
+ whole URB has been used and this shader state is not active. -->
+ <field name="VS URB Starting Address" start="57" end="63" type="uint"/>
<field name="VS URB Entry Allocation Size" start="48" end="56" type="uint"/>
<field name="VS Number of URB Entries" start="32" end="47" type="uint"/>
</instruction>
--
2.9.3
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