[Mesa-dev] [PATCH 3/4] i965: Use correct vs and gs size for gen6_upload_urb.
Rafael Antognolli
rafael.antognolli at intel.com
Fri May 19 16:02:45 UTC 2017
The documentation for SNB says that it expects a value [0,4] = [1,5], but we
don't really check whether the parameters are actually >= 1.
Additionally, on blorp we are calling gen6_upload_urb(gs_size = 0), which
causes it to be sent as -1, and that shouldn't be valid, but seems to be just
ignored. This patch fixes that before we convert the urb state emission to
genxml.
Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
---
src/mesa/drivers/dri/i965/gen6_urb.c | 4 ++--
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index e69a1df..8938035 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -78,8 +78,8 @@ gen6_upload_urb(struct brw_context *brw, unsigned vs_size,
devinfo->urb.min_entries[MESA_SHADER_VERTEX]);
assert(brw->urb.nr_vs_entries % 4 == 0);
assert(brw->urb.nr_gs_entries % 4 == 0);
- assert(vs_size <= 5);
- assert(gs_size <= 5);
+ assert(vs_size >= 1 && vs_size <= 5);
+ assert(gs_size >= 1 && gs_size <= 5);
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 7157420..5ee5435 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -169,7 +169,7 @@ blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
gen7_upload_urb(brw, vs_entry_size, false, false);
#else
- gen6_upload_urb(brw, vs_entry_size, false, 0);
+ gen6_upload_urb(brw, vs_entry_size, false, 1);
#endif
}
--
2.9.3
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