[Mesa-dev] [PATCH 4/4] radeonsi: add si_screen::has_ls_vgpr_init_bug

[Nicolai Hähnle]

For the series:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 07.11.2017 04:12, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> ---
>   src/gallium/drivers/radeonsi/si_pipe.c       | 2 ++
>   src/gallium/drivers/radeonsi/si_pipe.h       | 1 +
>   src/gallium/drivers/radeonsi/si_shader.c     | 3 +--
>   src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
>   4 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 1ca5ca3..391997d 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -1067,20 +1067,22 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
>   	sscreen->assume_no_z_fights =
>   		driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
>   	sscreen->commutative_blend_add =
>   		driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
>   	sscreen->clear_db_cache_before_clear =
>   		driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
>   	sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 &&
>   					    sscreen->b.family <= CHIP_POLARIS12) ||
>   					   sscreen->b.family == CHIP_VEGA10 ||
>   					   sscreen->b.family == CHIP_RAVEN;
> +	sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
> +					sscreen->b.family == CHIP_RAVEN;
>   
>   	if (sscreen->b.debug_flags & DBG(DPBB)) {
>   		sscreen->dpbb_allowed = true;
>   	} else {
>   		/* Only enable primitive binning on Raven by default. */
>   		sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
>   					!(sscreen->b.debug_flags & DBG(NO_DPBB));
>   	}
>   
>   	if (sscreen->b.debug_flags & DBG(DFSM)) {
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index ab82064..6be51bb 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -90,20 +90,21 @@ struct si_screen {
>   	unsigned			gs_table_depth;
>   	unsigned			tess_offchip_block_dw_size;
>   	bool				has_clear_state;
>   	bool				has_distributed_tess;
>   	bool				has_draw_indirect_multi;
>   	bool				has_out_of_order_rast;
>   	bool				assume_no_z_fights;
>   	bool				commutative_blend_add;
>   	bool				clear_db_cache_before_clear;
>   	bool				has_msaa_sample_loc_bug;
> +	bool				has_ls_vgpr_init_bug;
>   	bool				dpbb_allowed;
>   	bool				dfsm_allowed;
>   	bool				llvm_has_working_vgpr_indexing;
>   
>   	/* Whether shaders are monolithic (1-part) or separate (3-part). */
>   	bool				use_monolithic_shaders;
>   	bool				record_llvm_ir;
>   
>   	mtx_t			shader_parts_mutex;
>   	struct si_shader_part		*vs_prologs;
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
> index 6bc08dd..c95f8d7 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -6875,22 +6875,21 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx,
>   
>   	/* Create the function. */
>   	si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
>   	func = ctx->main_fn;
>   
>   	if (key->vs_prolog.num_merged_next_stage_vgprs) {
>   		if (!key->vs_prolog.is_monolithic)
>   			si_init_exec_from_input(ctx, 3, 0);
>   
>   		if (key->vs_prolog.as_ls &&
> -		    (ctx->screen->b.family == CHIP_VEGA10 ||
> -		     ctx->screen->b.family == CHIP_RAVEN)) {
> +		    ctx->screen->has_ls_vgpr_init_bug) {
>   			/* If there are no HS threads, SPI loads the LS VGPRs
>   			 * starting at VGPR 0. Shift them back to where they
>   			 * belong.
>   			 */
>   			LLVMValueRef has_hs_threads =
>   				LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
>   				    unpack_param(ctx, 3, 8, 8),
>   				    ctx->i32_0, "");
>   
>   			for (i = 4; i > 0; --i) {
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index b17828e..2d9fcfe 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -1275,21 +1275,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
>   		if (old_is_poly != new_is_poly) {
>   			sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
>   			si_mark_atom_dirty(sctx, &sctx->scissors.atom);
>   		}
>   
>   		sctx->current_rast_prim = rast_prim;
>   		sctx->do_update_shaders = true;
>   	}
>   
>   	if (sctx->tes_shader.cso &&
> -	    (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
> +	    sctx->screen->has_ls_vgpr_init_bug) {
>   		/* Determine whether the LS VGPR fix should be applied.
>   		 *
>   		 * It is only required when num input CPs > num output CPs,
>   		 * which cannot happen with the fixed function TCS. We should
>   		 * also update this bit when switching from TCS to fixed
>   		 * function TCS.
>   		 */
>   		struct si_shader_selector *tcs = sctx->tcs_shader.cso;
>   		bool ls_vgpr_fix =
>   			tcs &&
> 


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