[Mesa-dev] NIR linking optimisations for Gallium drivers

[Timothy Arceri]

On 22/11/17 07:28, Eric Anholt wrote:
> Timothy Arceri <tarceri at itsqueeze.com> writes:
> 
>> This series depends on:
>> https://patchwork.freedesktop.org/series/34131/
>>
>> Tested without regression on radeonsi.
>>
>> Shader-db results (still limited to GLSL 1.40 so not to interesting):
>>
>> Totals from affected shaders:
>> SGPRS: 29440 -> 30464 (3.48 %)
>> VGPRS: 19620 -> 19584 (-0.18 %)
>> Spilled SGPRs: 131 -> 129 (-1.53 %)
>> Spilled VGPRs: 0 -> 0 (0.00 %)
>> Private memory VGPRs: 0 -> 0 (0.00 %)
>> Scratch size: 0 -> 0 (0.00 %) dwords per thread
>> Code Size: 749312 -> 749548 (0.03 %) bytes
>> LDS: 0 -> 0 (0.00 %) blocks
>> Max Waves: 4751 -> 4767 (0.34 %)
>> Wait states: 0 -> 0 (0.00 %)
>>
>> The middle patches just move things around so that we can make use
>> of the linking opts, hopefully having them split up this much should
>> make regression testing easy for the existing gallium nir drivers.
> 
> I tried your radeonsi_nir_linking2 on vc4, and my shader-db results are:
> 
> total uniforms in shared programs: 26619 -> 26615 (-0.02%)
> uniforms in affected programs:     410 -> 406 (-0.98%)
> total max temps in shared programs: 9954 -> 9957 (0.03%)
> max temps in affected programs:     54 -> 57 (5.56%)
> total instructions in shared programs: 78142 -> 78174 (0.04%)
> instructions in affected programs:     7932 -> 7964 (0.40%)
> 
> So it looks like things are fine for me.  I think with this in place, I
> might be able to drop my dead code elimination and QIR rescheduling of
> varying loads (things that I don't have in the vc5 compiler currently).
> 

Thanks for testing :)

Rob you might want to give this branch [1] a test also.

[1] https://github.com/tarceri/Mesa.git radeonsi_nir_linking2