[Mesa-dev] [PATCH 2/6] ac/surface: enable DCC computation for MSAA

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_surface.c               | 6 ++----
 src/amd/vulkan/radv_image.c               | 3 ++-
 src/gallium/drivers/radeon/r600_texture.c | 3 ++-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 4db48cf..8347c45 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -579,21 +579,21 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	/* DCC notes:
 	 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 	 *   with samples >= 4.
 	 * - Mipmapped array textures have low performance (discovered by a closed
 	 *   driver team).
 	 */
 	AddrSurfInfoIn.flags.dccCompatible =
 		info->chip_class >= VI &&
 		!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
 		!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
-		!compressed && AddrDccIn.numSamples <= 1 &&
+		!compressed &&
 		((config->info.array_size == 1 && config->info.depth == 1) ||
 		 config->info.levels == 1);
 
 	AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
 	AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 
 	/* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
 	 * for Z and stencil. This can cause a number of problems which we work
 	 * around here:
 	 *
@@ -920,23 +920,21 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 		surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
 		surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
 		surf->htile_size = hout.htileBytes;
 		surf->htile_slice_size = hout.sliceSize;
 		surf->htile_alignment = hout.baseAlign;
 	} else {
 		/* DCC */
 		if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
 		    !(surf->flags & RADEON_SURF_SCANOUT) &&
 		    !compressed &&
-		    in->swizzleMode != ADDR_SW_LINEAR &&
-		    /* TODO: We could support DCC with MSAA. */
-		    in->numSamples == 1) {
+		    in->swizzleMode != ADDR_SW_LINEAR) {
 			ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
 			ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
 			ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
 
 			din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
 			dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
 			dout.pMipInfo = meta_mip_info;
 
 			din.dccKeyFlags.pipeAligned = 1;
 			din.dccKeyFlags.rbAligned = 1;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c241e36..b145e81 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -148,21 +148,22 @@ radv_init_surface(struct radv_device *device,
 		}
 	}
 
 	if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
 	                           VK_IMAGE_USAGE_STORAGE_BIT)) ||
 	    (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
 	    !dcc_compatible_formats ||
             (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
             pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
             device->physical_device->rad_info.chip_class < VI ||
-            create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC))
+            create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) ||
+	    pCreateInfo->samples >= 2)
 		surface->flags |= RADEON_SURF_DISABLE_DCC;
 	if (create_info->scanout)
 		surface->flags |= RADEON_SURF_SCANOUT;
 	return 0;
 }
 
 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
 {
 	return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
 }
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 933a4a9..0c30b62 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -259,21 +259,22 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 
 			flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
 		}
 
 		if (is_stencil)
 			flags |= RADEON_SURF_SBUFFER;
 	}
 
 	if (rscreen->chip_class >= VI &&
 	    (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
-	     ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
+	     ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
+	     ptex->nr_samples >= 2))
 		flags |= RADEON_SURF_DISABLE_DCC;
 
 	if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
 		/* This should catch bugs in gallium users setting incorrect flags. */
 		assert(ptex->nr_samples <= 1 &&
 		       ptex->array_size == 1 &&
 		       ptex->depth0 == 1 &&
 		       ptex->last_level == 0 &&
 		       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
-- 
2.7.4