[Mesa-dev] [PATCH 1/6] radeonsi: fix layered DCC fast clear

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Cc: 17.2 17.3 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeon/r600_texture.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 3fa5f5e..933a4a9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2478,22 +2478,25 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
 		dcc_offset = rtex->dcc_offset;
 	}
 
 	if (rctx->chip_class >= GFX9) {
 		/* Mipmap level clears aren't implemented. */
 		assert(rtex->resource.b.b.last_level == 0);
 		/* MSAA needs a different clear size. */
 		assert(rtex->resource.b.b.nr_samples <= 1);
 		clear_size = rtex->surface.dcc_size;
 	} else {
+		unsigned num_layers = util_max_layer(&rtex->resource.b.b, level) + 1;
+
 		dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
-		clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size;
+		clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
+			     num_layers;
 	}
 
 	rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset, clear_size,
 			   clear_value, R600_COHERENCY_CB_META);
 }
 
 /* Set the same micro tile mode as the destination of the last MSAA resolve.
  * This allows hitting the MSAA resolve fast path, which requires that both
  * src and dst micro tile modes match.
  */
-- 
2.7.4