[Mesa-dev] [PATCH 08/23] radeonsi: remove some definitions and helpers from r600_pipe_common.h
Marek Olšák
maraeo at gmail.com
Tue Nov 28 21:38:36 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 102 ----------------------
src/gallium/drivers/radeonsi/si_blit.c | 6 +-
src/gallium/drivers/radeonsi/si_clear.c | 2 +-
src/gallium/drivers/radeonsi/si_compute.c | 9 +-
src/gallium/drivers/radeonsi/si_cp_dma.c | 4 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 18 +++-
src/gallium/drivers/radeonsi/si_hw_context.c | 4 +-
src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h | 43 +++++++++
src/gallium/drivers/radeonsi/si_state.c | 46 ++++++++--
src/gallium/drivers/radeonsi/si_state_draw.c | 19 ++--
src/gallium/drivers/radeonsi/si_state_shaders.c | 4 +-
src/gallium/drivers/radeonsi/si_state_streamout.c | 2 +-
13 files changed, 125 insertions(+), 136 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 0982d1d..5fcaa10 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -39,40 +39,33 @@
#include "util/u_blitter.h"
#include "util/list.h"
#include "util/u_range.h"
#include "util/slab.h"
#include "util/u_suballoc.h"
#include "util/u_transfer.h"
#include "util/u_threaded_context.h"
struct u_log_context;
-#define ATI_VENDOR_ID 0x1002
-
#define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
/* Pipeline & streamout query controls. */
#define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
#define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
#define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
#define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
-/* special primitive types */
-#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
-
-#define R600_NOT_QUERY 0xffffffff
-
/* Debug flags. */
enum {
/* Shader logging options: */
DBG_VS = PIPE_SHADER_VERTEX,
DBG_PS = PIPE_SHADER_FRAGMENT,
DBG_GS = PIPE_SHADER_GEOMETRY,
DBG_TCS = PIPE_SHADER_TESS_CTRL,
DBG_TES = PIPE_SHADER_TESS_EVAL,
DBG_CS = PIPE_SHADER_COMPUTE,
DBG_NO_IR,
@@ -129,32 +122,20 @@ enum {
DBG_TEST_VMFAULT_SHADER,
};
#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
#define DBG(name) (1ull << DBG_##name)
#define R600_MAP_BUFFER_ALIGNMENT 64
#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
-enum r600_coherency {
- R600_COHERENCY_NONE, /* no cache flushes needed */
- R600_COHERENCY_SHADER,
- R600_COHERENCY_CB_META,
-};
-
-#ifdef PIPE_ARCH_BIG_ENDIAN
-#define R600_BIG_ENDIAN 1
-#else
-#define R600_BIG_ENDIAN 0
-#endif
-
struct r600_common_context;
struct r600_perfcounters;
struct tgsi_shader_info;
struct r600_qbo_state;
void si_radeon_shader_binary_init(struct ac_shader_binary *b);
void si_radeon_shader_binary_clean(struct ac_shader_binary *b);
/* Only 32-bit buffer allocations are supported, gallium doesn't support more
* at the moment.
@@ -780,103 +761,20 @@ r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
pipe_resource_reference((struct pipe_resource **)ptr,
(struct pipe_resource *)res);
}
static inline void
r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
{
pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
}
-static inline void
-r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
-{
- struct r600_common_context *rctx = (struct r600_common_context *)ctx;
- struct r600_resource *res = (struct r600_resource *)r;
-
- if (res) {
- /* Add memory usage for need_gfx_cs_space */
- rctx->vram += res->vram_usage;
- rctx->gtt += res->gart_usage;
- }
-}
-
-#define SQ_TEX_XY_FILTER_POINT 0x00
-#define SQ_TEX_XY_FILTER_BILINEAR 0x01
-#define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
-#define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
-
-static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
-{
- if (filter == PIPE_TEX_FILTER_LINEAR)
- return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
- : SQ_TEX_XY_FILTER_BILINEAR;
- else
- return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
- : SQ_TEX_XY_FILTER_POINT;
-}
-
-static inline unsigned r600_tex_aniso_filter(unsigned filter)
-{
- if (filter < 2)
- return 0;
- if (filter < 4)
- return 1;
- if (filter < 8)
- return 2;
- if (filter < 16)
- return 3;
- return 4;
-}
-
-static inline enum radeon_bo_priority
-r600_get_sampler_view_priority(struct r600_resource *res)
-{
- if (res->b.b.target == PIPE_BUFFER)
- return RADEON_PRIO_SAMPLER_BUFFER;
-
- if (res->b.b.nr_samples > 1)
- return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
-
- return RADEON_PRIO_SAMPLER_TEXTURE;
-}
-
-static inline bool
-r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
-{
- return (stencil_sampler && tex->can_sample_s) ||
- (!stencil_sampler && tex->can_sample_z);
-}
-
static inline bool
vi_dcc_enabled(struct r600_texture *tex, unsigned level)
{
return tex->dcc_offset && level < tex->surface.num_dcc_levels;
}
-static inline bool
-r600_htile_enabled(struct r600_texture *tex, unsigned level)
-{
- return tex->htile_offset && level == 0;
-}
-
-static inline bool
-vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
-{
- assert(!tex->tc_compatible_htile || tex->htile_offset);
- return tex->tc_compatible_htile && level == 0;
-}
-
-#define COMPUTE_DBG(rscreen, fmt, args...) \
- do { \
- if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
- } while (0);
-
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
-static inline int S_FIXED(float value, unsigned frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
#endif
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 2f7c2be..0e314e9 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -308,31 +308,31 @@ si_decompress_depth(struct si_context *sctx,
unsigned inplace_planes = 0;
unsigned copy_planes = 0;
unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
unsigned levels_z = 0;
unsigned levels_s = 0;
if (required_planes & PIPE_MASK_Z) {
levels_z = level_mask & tex->dirty_level_mask;
if (levels_z) {
- if (r600_can_sample_zs(tex, false))
+ if (si_can_sample_zs(tex, false))
inplace_planes |= PIPE_MASK_Z;
else
copy_planes |= PIPE_MASK_Z;
}
}
if (required_planes & PIPE_MASK_S) {
levels_s = level_mask & tex->stencil_dirty_level_mask;
if (levels_s) {
- if (r600_can_sample_zs(tex, true))
+ if (si_can_sample_zs(tex, true))
inplace_planes |= PIPE_MASK_S;
else
copy_planes |= PIPE_MASK_S;
}
}
if (unlikely(sctx->b.log))
u_log_printf(sctx->b.log,
"\n------------------------------------------------\n"
"Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
@@ -367,21 +367,21 @@ si_decompress_depth(struct si_context *sctx,
first_layer, last_layer,
0, u_max_sample(&tex->resource.b.b));
if (copy_planes & PIPE_MASK_Z)
tex->dirty_level_mask &= ~fully_copied_levels;
if (copy_planes & PIPE_MASK_S)
tex->stencil_dirty_level_mask &= ~fully_copied_levels;
}
if (inplace_planes) {
- bool has_htile = r600_htile_enabled(tex, first_level);
+ bool has_htile = si_htile_enabled(tex, first_level);
bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
/* Don't decompress if there is no HTILE or when HTILE is
* TC-compatible. */
if (has_htile && !tc_compat_htile) {
si_blit_decompress_zs_in_place(
sctx, tex,
levels_z, levels_s,
first_layer, last_layer);
} else {
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 4663fc2..634d4cc 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -544,21 +544,21 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
if (!fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
if (tex->fmask.size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
}
if (zstex &&
- r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
+ si_htile_enabled(zstex, zsbuf->u.tex.level) &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
(!zstex->tc_compatible_htile ||
depth == 0 || depth == 1)) {
/* Need to disable EXPCLEAR temporarily if clearing
* to a new value. */
if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
sctx->db_depth_disable_expclear = true;
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index cf4a88b..dc40989 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -26,20 +26,25 @@
#include "util/u_async_debug.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
#include "amd_kernel_code_t.h"
#include "radeon/r600_cs.h"
#include "si_pipe.h"
#include "si_compute.h"
#include "sid.h"
+#define COMPUTE_DBG(rscreen, fmt, args...) \
+ do { \
+ if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
+ } while (0);
+
struct dispatch_packet {
uint16_t header;
uint16_t setup;
uint16_t workgroup_size_x;
uint16_t workgroup_size_y;
uint16_t workgroup_size_z;
uint16_t reserved0;
uint32_t grid_size_x;
uint32_t grid_size_y;
uint32_t grid_size_z;
@@ -806,25 +811,25 @@ static void si_launch_grid(
return;
if (sctx->b.last_num_draw_calls != sctx->b.num_draw_calls) {
si_update_fb_dirtiness_after_rendering(sctx);
sctx->b.last_num_draw_calls = sctx->b.num_draw_calls;
}
si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
/* Add buffer sizes for memory checking in need_cs_space. */
- r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
+ si_context_add_resource_size(ctx, &program->shader.bo->b.b);
/* TODO: add the scratch buffer */
if (info->indirect) {
- r600_context_add_resource_size(ctx, info->indirect);
+ si_context_add_resource_size(ctx, info->indirect);
/* Indirect buffers use TC L2 on GFX9, but not older hw. */
if (sctx->b.chip_class <= VI &&
r600_resource(info->indirect)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(info->indirect)->TC_L2_dirty = false;
}
}
si_need_cs_space(sctx);
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 5582471..446ff2c 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -158,23 +158,23 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
bool *is_first, unsigned *packet_flags)
{
/* Fast exit for a CPDMA prefetch. */
if ((user_flags & SI_CPDMA_SKIP_ALL) == SI_CPDMA_SKIP_ALL) {
*is_first = false;
return;
}
if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
/* Count memory usage in so that need_cs_space can take it into account. */
- r600_context_add_resource_size(&sctx->b.b, dst);
+ si_context_add_resource_size(&sctx->b.b, dst);
if (src)
- r600_context_add_resource_size(&sctx->b.b, src);
+ si_context_add_resource_size(&sctx->b.b, src);
}
if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
si_need_cs_space(sctx);
/* This must be done after need_cs_space. */
if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource*)dst,
RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 471c93a..e91f923 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -192,20 +192,32 @@ si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc
{
if (!desc->buffer)
return;
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
}
/* SAMPLER VIEWS */
+static inline enum radeon_bo_priority
+si_get_sampler_view_priority(struct r600_resource *res)
+{
+ if (res->b.b.target == PIPE_BUFFER)
+ return RADEON_PRIO_SAMPLER_BUFFER;
+
+ if (res->b.b.nr_samples > 1)
+ return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
+
+ return RADEON_PRIO_SAMPLER_TEXTURE;
+}
+
static unsigned
si_sampler_and_image_descriptors_idx(unsigned shader)
{
return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
}
static struct si_descriptors *
si_sampler_and_image_descriptors(struct si_context *sctx, unsigned shader)
{
@@ -230,26 +242,26 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
struct r600_resource *rres;
struct r600_texture *rtex;
enum radeon_bo_priority priority;
if (!resource)
return;
if (resource->target != PIPE_BUFFER) {
struct r600_texture *tex = (struct r600_texture*)resource;
- if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
+ if (tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
resource = &tex->flushed_depth_texture->resource.b.b;
}
rres = (struct r600_resource*)resource;
- priority = r600_get_sampler_view_priority(rres);
+ priority = si_get_sampler_view_priority(rres);
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rres, usage, priority,
check_mem);
if (resource->target == PIPE_BUFFER)
return;
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
@@ -299,21 +311,21 @@ static void si_set_buf_desc_address(struct r600_resource *buf,
*/
void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
struct r600_texture *tex,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state)
{
uint64_t va, meta_va = 0;
- if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
+ if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) {
tex = tex->flushed_depth_texture;
is_stencil = false;
}
va = tex->resource.gpu_address;
if (sscreen->b.chip_class >= GFX9) {
/* Only stencil_offset needs to be added here. */
if (is_stencil)
va += tex->surface.u.gfx9.stencil_offset;
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 1903cf8..2d7f6a7 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -258,22 +258,22 @@ void si_begin_new_cs(struct si_context *ctx)
si_all_resident_buffers_begin_new_cs(ctx);
ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
si_mark_atom_dirty(ctx, &ctx->viewports.atom);
si_mark_atom_dirty(ctx, &ctx->scratch_state);
if (ctx->scratch_buffer) {
- r600_context_add_resource_size(&ctx->b.b,
- &ctx->scratch_buffer->b.b);
+ si_context_add_resource_size(&ctx->b.b,
+ &ctx->scratch_buffer->b.b);
}
if (ctx->streamout.suspended) {
ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
si_streamout_buffers_dirty(ctx);
}
si_postflush_resume_features(&ctx->b);
assert(!ctx->b.gfx.cs->prev_dw);
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 5029af0..b742967 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -605,21 +605,21 @@ static void si_pc_emit_start(struct r600_common_context *ctx,
/* Note: The buffer was already added in si_pc_emit_start, so we don't have to
* do it again in here. */
static void si_pc_emit_stop(struct r600_common_context *ctx,
struct r600_resource *buffer, uint64_t va)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
- buffer, va, 0, R600_NOT_QUERY);
+ buffer, va, 0, SI_NOT_QUERY);
si_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
S_036020_PERFMON_SAMPLE_ENABLE(1));
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index c0846f4..fd9ba3a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -27,20 +27,24 @@
#include "util/u_dynarray.h"
#include "util/u_idalloc.h"
#ifdef PIPE_ARCH_BIG_ENDIAN
#define SI_BIG_ENDIAN 1
#else
#define SI_BIG_ENDIAN 0
#endif
+#define ATI_VENDOR_ID 0x1002
+
+#define SI_NOT_QUERY 0xffffffff
+
/* The base vertex and primitive restart can be any number, but we must pick
* one which will mean "unknown" for the purpose of state tracking and
* the number shouldn't be a commonly-used one. */
#define SI_BASE_VERTEX_UNKNOWN INT_MIN
#define SI_RESTART_INDEX_UNKNOWN INT_MIN
#define SI_NUM_SMOOTH_AA_SAMPLES 8
#define SI_GS_PER_ES 128
/* Alignment for optimal CP DMA performance. */
#define SI_CPDMA_ALIGNMENT 32
@@ -589,20 +593,26 @@ void si_init_clear_functions(struct si_context *sctx);
#define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
#define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
#define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
#define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
#define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
SI_CPDMA_SKIP_SYNC_AFTER | \
SI_CPDMA_SKIP_SYNC_BEFORE | \
SI_CPDMA_SKIP_GFX_SYNC | \
SI_CPDMA_SKIP_BO_LIST_UPDATE)
+enum r600_coherency {
+ R600_COHERENCY_NONE, /* no cache flushes needed */
+ R600_COHERENCY_SHADER,
+ R600_COHERENCY_CB_META,
+};
+
void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher);
void si_copy_buffer(struct si_context *sctx,
struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size,
unsigned user_flags);
void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
uint64_t offset, unsigned size);
void cik_emit_prefetch_L2(struct si_context *sctx);
@@ -653,20 +663,33 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
/* si_viewport.c */
void si_update_vs_viewport_state(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
/*
* common helpers
*/
static inline void
+si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+ struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ struct r600_resource *res = (struct r600_resource *)r;
+
+ if (res) {
+ /* Add memory usage for need_gfx_cs_space */
+ rctx->vram += res->vram_usage;
+ rctx->gtt += res->gart_usage;
+ }
+}
+
+static inline void
si_invalidate_draw_sh_constants(struct si_context *sctx)
{
sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
}
static inline void
si_set_atom_dirty(struct si_context *sctx,
struct r600_atom *atom, bool dirty)
{
unsigned bit = 1 << atom->id;
@@ -786,11 +809,31 @@ si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
if (num_samples >= 2 || include_stencil)
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
else if (shaders_read_metadata)
sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
} else {
/* SI-CI-VI */
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
}
+static inline bool
+si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
+{
+ return (stencil_sampler && tex->can_sample_s) ||
+ (!stencil_sampler && tex->can_sample_z);
+}
+
+static inline bool
+si_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+ return tex->htile_offset && level == 0;
+}
+
+static inline bool
+vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+ assert(!tex->tc_compatible_htile || tex->htile_offset);
+ return tex->tc_compatible_htile && level == 0;
+}
+
#endif
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d59b363..ca32afd 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2524,21 +2524,21 @@ static void si_init_depth_surface(struct si_context *sctx,
S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
S_028038_MAXMIP(rtex->resource.b.b.last_level);
s_info = S_02803C_FORMAT(stencil_format) |
S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
surf->db_depth_view |= S_028008_MIPID(level);
surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
- if (r600_htile_enabled(rtex, level)) {
+ if (si_htile_enabled(rtex, level)) {
z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
S_028038_ALLOW_EXPCLEAR(1);
if (rtex->tc_compatible_htile) {
unsigned max_zplanes = 4;
if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
rtex->resource.b.b.nr_samples > 1)
max_zplanes = 2;
@@ -2602,21 +2602,21 @@ static void si_init_depth_surface(struct si_context *sctx,
z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
tile_mode_index = si_tile_mode_index(rtex, level, true);
s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
}
surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
levelinfo->nblk_y) / 64 - 1);
- if (r600_htile_enabled(rtex, level)) {
+ if (si_htile_enabled(rtex, level)) {
z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
S_028040_ALLOW_EXPCLEAR(1);
if (rtex->surface.has_stencil) {
/* Workaround: For a not yet understood reason, the
* combination of MSAA, fast stencil clear and stencil
* decompress messes with subsequent stencil buffer
* uses. Problem was reproduced on Verde, Bonaire,
* Tonga, and Carrizo.
*
@@ -2854,21 +2854,21 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
if (rtex->fmask.size) {
sctx->framebuffer.compressed_cb_mask |= 1 << i;
}
if (rtex->surface.is_linear)
sctx->framebuffer.any_dst_linear = true;
if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
sctx->framebuffer.CB_has_shader_readable_metadata = true;
- r600_context_add_resource_size(ctx, surf->base.texture);
+ si_context_add_resource_size(ctx, surf->base.texture);
p_atomic_inc(&rtex->framebuffers_bound);
if (rtex->dcc_gather_statistics) {
/* Dirty tracking must be enabled for DCC usage analysis. */
sctx->framebuffer.compressed_cb_mask |= 1 << i;
vi_separate_dcc_start_query(ctx, rtex);
}
}
@@ -2878,21 +2878,21 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
surf = (struct r600_surface*)state->zsbuf;
zstex = (struct r600_texture*)surf->base.texture;
if (!surf->depth_initialized) {
si_init_depth_surface(sctx, surf);
}
if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
sctx->framebuffer.DB_has_shader_readable_metadata = true;
- r600_context_add_resource_size(ctx, surf->base.texture);
+ si_context_add_resource_size(ctx, surf->base.texture);
}
si_update_poly_offset_state(sctx);
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
if (sctx->screen->dpbb_allowed)
si_mark_atom_dirty(sctx, &sctx->dpbb_state);
if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
@@ -3886,21 +3886,21 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
if (state->target == PIPE_TEXTURE_1D ||
state->target == PIPE_TEXTURE_2D ||
state->target == PIPE_TEXTURE_RECT ||
state->target == PIPE_TEXTURE_CUBE)
last_layer = state->u.tex.first_layer;
/* Texturing with separate depth and stencil. */
pipe_format = state->format;
/* Depth/stencil texturing sometimes needs separate texture. */
- if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
+ if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
if (!tmp->flushed_depth_texture &&
!si_init_flushed_depth_texture(ctx, texture, NULL)) {
pipe_resource_reference(&view->base.texture, NULL);
FREE(view);
return NULL;
}
assert(tmp->flushed_depth_texture);
/* Override format for the case where the flushed texture
@@ -4046,29 +4046,57 @@ do { \
sizeof(*color));
util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
color, sizeof(*color));
sctx->border_color_count++;
}
return S_008F3C_BORDER_COLOR_PTR(i) |
S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
}
+static inline int S_FIXED(float value, unsigned frac_bits)
+{
+ return value * (1 << frac_bits);
+}
+
+static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
+{
+ if (filter == PIPE_TEX_FILTER_LINEAR)
+ return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
+ : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
+ else
+ return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
+ : V_008F38_SQ_TEX_XY_FILTER_POINT;
+}
+
+static inline unsigned si_tex_aniso_filter(unsigned filter)
+{
+ if (filter < 2)
+ return 0;
+ if (filter < 4)
+ return 1;
+ if (filter < 8)
+ return 2;
+ if (filter < 16)
+ return 3;
+ return 4;
+}
+
static void *si_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
struct si_context *sctx = (struct si_context *)ctx;
struct r600_common_screen *rscreen = sctx->b.screen;
struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
: state->max_anisotropy;
- unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
+ unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
union pipe_color_union clamped_border_color;
if (!rstate) {
return NULL;
}
#ifdef DEBUG
rstate->magic = SI_SAMPLER_STATE_MAGIC;
#endif
rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
@@ -4078,22 +4106,22 @@ static void *si_create_sampler_state(struct pipe_context *ctx,
S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
S_008F30_ANISO_BIAS(max_aniso_ratio) |
S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
- S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
- S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
+ S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
+ S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
S_008F38_MIP_POINT_PRECLAMP(0) |
S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
S_008F38_FILTER_PREC_FIX(1) |
S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
/* Create sampler resource for integer textures. */
memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
@@ -4358,21 +4386,21 @@ static void si_set_vertex_buffers(struct pipe_context *ctx,
if (buffers) {
for (i = 0; i < count; i++) {
const struct pipe_vertex_buffer *src = buffers + i;
struct pipe_vertex_buffer *dsti = dst + i;
struct pipe_resource *buf = src->buffer.resource;
pipe_resource_reference(&dsti->buffer.resource, buf);
dsti->buffer_offset = src->buffer_offset;
dsti->stride = src->stride;
- r600_context_add_resource_size(ctx, buf);
+ si_context_add_resource_size(ctx, buf);
if (buf)
r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
}
} else {
for (i = 0; i < count; i++) {
pipe_resource_reference(&dst[i].buffer.resource, NULL);
}
}
sctx->vertex_buffers_dirty = true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 53f33ca..530137e 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -26,39 +26,42 @@
#include "sid.h"
#include "gfx9d.h"
#include "util/u_index_modify.h"
#include "util/u_log.h"
#include "util/u_upload_mgr.h"
#include "util/u_prim.h"
#include "ac_debug.h"
+/* special primitive types */
+#define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
+
static unsigned si_conv_pipe_prim(unsigned mode)
{
static const unsigned prim_conv[] = {
[PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
[PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
[PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
[PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
[PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
[PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
[PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
[PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
[PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
[PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
[PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
[PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
[PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
[PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
- [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
+ [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
};
assert(mode < ARRAY_SIZE(prim_conv));
return prim_conv[mode];
}
static unsigned si_conv_prim_to_gs_out(unsigned mode)
{
static const int prim_conv[] = {
[PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
[PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
@@ -68,21 +71,21 @@ static unsigned si_conv_prim_to_gs_out(unsigned mode)
[PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
[PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
[PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
[PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
- [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
+ [SI_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
};
assert(mode < ARRAY_SIZE(prim_conv));
return prim_conv[mode];
}
/**
* This calculates the LDS size for tessellation shaders (VS, TCS, TES).
* LS.LDS_SIZE is shared by all 3 shader stages.
*
@@ -304,21 +307,21 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
else
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
ls_hs_config);
}
static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
{
switch (info->mode) {
case PIPE_PRIM_PATCHES:
return info->count / info->vertices_per_patch;
- case R600_PRIM_RECTANGLE_LIST:
+ case SI_PRIM_RECTANGLE_LIST:
return info->count / 3;
default:
return u_prims_for_vertices(info->mode, info->count);
}
}
static unsigned
si_get_init_multi_vgt_param(struct si_screen *sscreen,
union si_vgt_param_key *key)
{
@@ -439,21 +442,21 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
max_primgroup_in_wave : 0) |
S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
}
void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
{
- for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
+ for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
for (int multi_instances = 0; multi_instances < 2; multi_instances++)
for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
for (int count_from_so = 0; count_from_so < 2; count_from_so++)
for (int line_stipple = 0; line_stipple < 2; line_stipple++)
for (int uses_tess = 0; uses_tess < 2; uses_tess++)
for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
union si_vgt_param_key key;
@@ -900,21 +903,21 @@ void si_emit_cache_flush(struct si_context *sctx)
S_0085F0_CB3_DEST_BASE_ENA(1) |
S_0085F0_CB4_DEST_BASE_ENA(1) |
S_0085F0_CB5_DEST_BASE_ENA(1) |
S_0085F0_CB6_DEST_BASE_ENA(1) |
S_0085F0_CB7_DEST_BASE_ENA(1);
/* Necessary for DCC */
if (rctx->chip_class == VI)
si_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0, EOP_DATA_SEL_DISCARD, NULL,
- 0, 0, R600_NOT_QUERY);
+ 0, 0, SI_NOT_QUERY);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
S_0085F0_DB_DEST_BASE_ENA(1);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
/* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
@@ -1016,21 +1019,21 @@ void si_emit_cache_flush(struct si_context *sctx)
sctx->b.num_L2_invalidates++;
}
/* Do the flush (enqueue the event and wait for it). */
va = sctx->wait_mem_scratch->gpu_address;
sctx->wait_mem_number++;
si_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
EOP_DATA_SEL_VALUE_32BIT,
sctx->wait_mem_scratch, va,
- sctx->wait_mem_number, R600_NOT_QUERY);
+ sctx->wait_mem_number, SI_NOT_QUERY);
si_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
}
/* Make sure ME is idle (it executes most packets) before continuing.
* This prevents read-after-write hazards between PFP and ME.
*/
if (cp_coher_cntl ||
(rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2 |
@@ -1372,21 +1375,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
* need this. */
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indexbuf)->TC_L2_dirty = false;
}
}
if (info->indirect) {
struct pipe_draw_indirect_info *indirect = info->indirect;
/* Add the buffer size for memory checking in need_cs_space. */
- r600_context_add_resource_size(ctx, indirect->buffer);
+ si_context_add_resource_size(ctx, indirect->buffer);
/* Indirect buffers use TC L2 on GFX9, but not older hw. */
if (sctx->b.chip_class <= VI) {
if (r600_resource(indirect->buffer)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indirect->buffer)->TC_L2_dirty = false;
}
if (indirect->indirect_draw_count &&
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
@@ -1529,21 +1532,21 @@ void si_draw_rectangle(struct blitter_context *blitter,
case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
sizeof(attrib->texcoord));
break;
case UTIL_BLITTER_ATTRIB_NONE:;
}
pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
struct pipe_draw_info info = {};
- info.mode = R600_PRIM_RECTANGLE_LIST;
+ info.mode = SI_PRIM_RECTANGLE_LIST;
info.count = 3;
info.instance_count = num_instances;
/* Don't set per-stage shader pointers for VS. */
sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
sctx->vertex_buffer_pointer_dirty = false;
si_draw_vbo(pipe, &info);
}
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 3edc340..513e30b 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3022,22 +3022,22 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
sctx->scratch_buffer = (struct r600_resource*)
si_aligned_buffer_create(&sctx->screen->b.b,
R600_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
if (!sctx->scratch_buffer)
return false;
si_mark_atom_dirty(sctx, &sctx->scratch_state);
- r600_context_add_resource_size(&sctx->b.b,
- &sctx->scratch_buffer->b.b);
+ si_context_add_resource_size(&sctx->b.b,
+ &sctx->scratch_buffer->b.b);
}
if (!si_update_scratch_relocs(sctx))
return false;
}
/* The LLVM shader backend should be reporting aligned scratch_sizes. */
assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
"scratch size should already be aligned correctly.");
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 3d1d9dc..0c20c58 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -145,21 +145,21 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
if (sctx->streamout.num_targets && sctx->streamout.begin_emitted)
si_emit_streamout_end(sctx);
/* Set the new targets. */
unsigned enabled_mask = 0, append_bitmask = 0;
for (i = 0; i < num_targets; i++) {
si_so_target_reference(&sctx->streamout.targets[i], targets[i]);
if (!targets[i])
continue;
- r600_context_add_resource_size(ctx, targets[i]->buffer);
+ si_context_add_resource_size(ctx, targets[i]->buffer);
enabled_mask |= 1 << i;
if (offsets[i] == ((unsigned)-1))
append_bitmask |= 1 << i;
}
for (; i < sctx->streamout.num_targets; i++)
si_so_target_reference(&sctx->streamout.targets[i], NULL);
sctx->streamout.enabled_mask = enabled_mask;
--
2.7.4
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