[Mesa-dev] [PATCH 2/2] radv: Disallow indirect outputs for GS on GFX9 as well.
Andres Gomez
agomez at igalia.com
Fri Oct 27 15:03:05 UTC 2017
Bas, this patch looks like it should have been marked as fixing
6ce550453f1 instead of e38685cc62e (?).
In any case, I was wondering whether it would be interesting to bring
them both to the 17.2 stable queue and whether we would also want
Timothy's preceding patch:
087e010b2b3dd83a539f97203909d6c43b5da87c radv: copy indirect lowering settings from radeonsi
Let me know what you think.
On Sun, 2017-10-22 at 18:43 +0200, Bas Nieuwenhuizen wrote:
> Since it also uses the output vector before writing to memory.
>
> Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
> ---
> src/amd/vulkan/radv_shader.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 07e68d6032b..6176a2e590d 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -265,9 +265,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
> indirect_mask |= nir_var_shader_in;
> }
> if (!llvm_has_working_vgpr_indexing &&
> - (nir->info.stage == MESA_SHADER_VERTEX ||
> - nir->info.stage == MESA_SHADER_TESS_EVAL ||
> - nir->info.stage == MESA_SHADER_FRAGMENT))
> + nir->info.stage != MESA_SHADER_TESS_CTRL)
> indirect_mask |= nir_var_shader_out;
>
> /* TODO: We shouldn't need to do this, however LLVM isn't currently
--
Br,
Andres
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