[Mesa-dev] [PATCH 3/3] i965: Disable stencil cache optimization combining two 4x2 blocks

[Kenneth Graunke]

On Monday, September 11, 2017 5:48:26 AM PDT Topi Pohjolainen wrote:
> From the BDW PRM, Volume 15, Workarounds:
> 
> KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.
> 
> W/A: Disable 4x4 RCPFE STC optimization and therefore only send one
>      valid 4x4 to STC on 4x4 interface. This will require setting bit
>      6 of reg. 0x7004. Must be done at boot and all save/restore paths.
> 
> From the SKL PRM, Volume 16, Workarounds:
> 
> 0556 KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.
> 
> W/A: Disable 4 x4 RCPFE STC optimization and therefore only send
>      one valid 4x4 to STC on 4x4 interface.  This will require setting
>      bit 6 of reg. 0x7004. Must be done at boot and all save/restore
>      paths.

The kernel has already implemented this workaround since v4.1 for Skylake,
v4.0 for Cherryview, and maybe v3.18 or older for Broadwell.  So I don't
think there's any need for us to do it in Mesa (and the text you quoted
makes me wonder whether it'd even work to do it from userspace).

--Ken
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