[Mesa-dev] [PATCH 3/3] i965: Disable stencil cache optimization combining two 4x2 blocks

[Chad Versace]

On Mon 11 Sep 2017, Topi Pohjolainen wrote:
> From the BDW PRM, Volume 15, Workarounds:
> 
> KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.
> 
> W/A: Disable 4x4 RCPFE STC optimization and therefore only send one
>      valid 4x4 to STC on 4x4 interface. This will require setting bit
>      6 of reg. 0x7004. Must be done at boot and all save/restore paths.
> 
> From the SKL PRM, Volume 16, Workarounds:
> 
> 0556 KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.
> 
> W/A: Disable 4 x4 RCPFE STC optimization and therefore only send
>      one valid 4x4 to STC on 4x4 interface.  This will require setting
>      bit 6 of reg. 0x7004. Must be done at boot and all save/restore
>      paths.
> 
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h      | 5 ++++-
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
>  2 files changed, 5 insertions(+), 1 deletion(-)

Acked-by: Chad Versace <chadversary at chromium.org>