[Mesa-dev] [PATCH] gallium/radeon: consolidate PIPE_BIND_SHARED/SCANOUT handling

Nicolai Hähnle nhaehnle at gmail.com
Wed Sep 20 13:58:06 UTC 2017


Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 18.09.2017 18:07, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> ---
>   src/gallium/drivers/radeon/r600_buffer_common.c | 13 ++++---------
>   src/gallium/drivers/radeon/r600_texture.c       |  4 ----
>   2 files changed, 4 insertions(+), 13 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index 706c748..b3e60a4 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -160,48 +160,43 @@ void si_init_resource_fields(struct r600_common_screen *rscreen,
>   	}
>   
>   	/* Tiled textures are unmappable. Always put them in VRAM. */
>   	if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
>   	    res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
>   		res->domains = RADEON_DOMAIN_VRAM;
>   		res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>   			 RADEON_FLAG_GTT_WC;
>   	}
>   
> -	/* Only displayable single-sample textures can be shared between
> -	 * processes. */
> -	if (!(res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT)) &&
> -	    (res->b.b.target == PIPE_BUFFER ||
> -	     res->b.b.nr_samples >= 2 ||
> -	     rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY))
> +	/* Displayable and shareable surfaces are not suballocated. */
> +	if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
> +		res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
> +	else
>   		res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
>   
>   	/* If VRAM is just stolen system memory, allow both VRAM and
>   	 * GTT, whichever has free space. If a buffer is evicted from
>   	 * VRAM to GTT, it will stay there.
>   	 *
>   	 * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
>   	 * placements even with a low amount of stolen VRAM.
>   	 */
>   	if (!rscreen->info.has_dedicated_vram &&
>   	    (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
>   	    res->domains == RADEON_DOMAIN_VRAM) {
>   		res->domains = RADEON_DOMAIN_VRAM_GTT;
>   		res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
>   	}
>   
>   	if (rscreen->debug_flags & DBG_NO_WC)
>   		res->flags &= ~RADEON_FLAG_GTT_WC;
>   
> -	if (res->b.b.bind & PIPE_BIND_SHARED)
> -		res->flags |= RADEON_FLAG_NO_SUBALLOC;
> -
>   	/* Set expected VRAM and GART usage for the buffer. */
>   	res->vram_usage = 0;
>   	res->gart_usage = 0;
>   
>   	if (res->domains & RADEON_DOMAIN_VRAM)
>   		res->vram_usage = size;
>   	else if (res->domains & RADEON_DOMAIN_GTT)
>   		res->gart_usage = size;
>   }
>   
> diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
> index f7b9740..b43ccdc 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1212,24 +1212,20 @@ r600_texture_create_object(struct pipe_screen *screen,
>   			rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
>   			rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
>   		}
>   	}
>   
>   	/* Now create the backing buffer. */
>   	if (!buf) {
>   		si_init_resource_fields(rscreen, resource, rtex->size,
>   					  rtex->surface.surf_alignment);
>   
> -		/* Displayable surfaces are not suballocated. */
> -		if (resource->b.b.bind & PIPE_BIND_SCANOUT)
> -			resource->flags |= RADEON_FLAG_NO_SUBALLOC;
> -
>   		if (!si_alloc_resource(rscreen, resource)) {
>   			FREE(rtex);
>   			return NULL;
>   		}
>   	} else {
>   		resource->buf = buf;
>   		resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
>   		resource->bo_size = buf->size;
>   		resource->bo_alignment = buf->alignment;
>   		resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
> 


-- 
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.


More information about the mesa-dev mailing list