[Mesa-dev] [PATCH 3/3] radeonsi: move descriptor logs to after corresponding draw/compute packet

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

It has to happen after descriptor uploads since otherwise we'll print out
the wrong GPU list / incorrectly claim descriptor corruption.
---
 src/gallium/drivers/radeonsi/si_compute.c    | 7 +++----
 src/gallium/drivers/radeonsi/si_state_draw.c | 7 +++----
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index ca334949d77..2346e2e95bc 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -799,23 +799,20 @@ static void si_launch_grid(
 		/* Indirect buffers use TC L2 on GFX9, but not older hw. */
 		if (sctx->b.chip_class <= VI &&
 		    r600_resource(info->indirect)->TC_L2_dirty) {
 			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 			r600_resource(info->indirect)->TC_L2_dirty = false;
 		}
 	}
 
 	si_need_cs_space(sctx);
 
-	if (sctx->b.log)
-		si_log_compute_state(sctx, sctx->b.log);
-
 	if (!sctx->cs_shader_state.initialized)
 		si_initialize_compute(sctx);
 
 	if (sctx->b.flags)
 		si_emit_cache_flush(sctx);
 
 	if (!si_switch_compute_shader(sctx, program, &program->shader,
 					code_object, info->pc))
 		return;
 
@@ -844,22 +841,24 @@ static void si_launch_grid(
 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 					  RADEON_USAGE_READWRITE,
 					  RADEON_PRIO_COMPUTE_GLOBAL);
 	}
 
 	if (program->ir_type == PIPE_SHADER_IR_TGSI)
 		si_setup_tgsi_grid(sctx, info);
 
 	si_emit_dispatch_packets(sctx, info);
 
-	if (unlikely(sctx->current_saved_cs))
+	if (unlikely(sctx->current_saved_cs)) {
 		si_trace_emit(sctx);
+		si_log_compute_state(sctx, sctx->b.log);
+	}
 
 	sctx->compute_is_busy = true;
 	sctx->b.num_compute_calls++;
 	if (sctx->cs_shader_state.uses_scratch)
 		sctx->b.num_spill_compute_calls++;
 
 	if (cs_regalloc_hang)
 		sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 05ed85475bf..e29d716580a 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1369,23 +1369,20 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 			if (indirect->indirect_draw_count &&
 			    r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
 				sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 				r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
 			}
 		}
 	}
 
 	si_need_cs_space(sctx);
 
-	if (unlikely(sctx->b.log))
-		si_log_draw_state(sctx, sctx->b.log);
-
 	/* Since we've called r600_context_add_resource_size for vertex buffers,
 	 * this must be called after si_need_cs_space, because we must let
 	 * need_cs_space flush before we add buffers to the buffer list.
 	 */
 	if (!si_upload_vertex_buffer_descriptors(sctx))
 		return;
 
 	/* GFX9 scissor bug workaround. This must be done before VPORT scissor
 	 * registers are changed. There is also a more efficient but more
 	 * involved alternative workaround.
@@ -1447,22 +1444,24 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask)
 			cik_emit_prefetch_L2(sctx);
 
 		if (!si_upload_graphics_shader_descriptors(sctx))
 			return;
 
 		si_emit_all_states(sctx, info, 0);
 		si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
 	}
 
-	if (unlikely(sctx->current_saved_cs))
+	if (unlikely(sctx->current_saved_cs)) {
 		si_trace_emit(sctx);
+		si_log_draw_state(sctx, sctx->b.log);
+	}
 
 	/* Workaround for a VGT hang when streamout is enabled.
 	 * It must be done after drawing. */
 	if ((sctx->b.family == CHIP_HAWAII ||
 	     sctx->b.family == CHIP_TONGA ||
 	     sctx->b.family == CHIP_FIJI) &&
 	    r600_get_strmout_en(&sctx->b)) {
 		sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
 	}
 
-- 
2.11.0