[Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

[Marek Olšák]

Hi,

This series removes the limitation that only ADDR registers are
allowed as address operands. Any 1D register can be an address
operand (IN, OUT, TEMP, SV, CONST reading from the first buffer slot).

Requirements:
- The address operand must be integer.
- The address operand must be a 1D register (with the exception of
  CONST that is allowed not to specify the second index in this case).
  2D registers aren't allowed, because TGSI doesn't support 2D
  registers as address operands.
- The address operand must not use indirect indexing within itself.

If all requirements are met, UARL isn't emitted and the source operand
of UARL is folded into the instruction where ADDR would normally be
used.

The use case that we primarily care about is to get SV[i].x in address
operands to help us generate better code in radeonsi.

Please review.

Thanks,
Marek