[Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

[Roland Scheidegger]

I think it's kind of a pity that there's no "intermediate" step here - I
think just about every modern driver doesn't want to see UARL / address
reg, but I'd assume not everybody can use _any_ 1d reg for addressing.
d3d10 only supports temp registers as addressing operands which looks
quite reasonable to me (since a address reg is pretty much the same as a
temp reg, just being temporary r/w storage) (and this is what softpipe
and llvmpipe can do), excluding inputs/outputs.
I realize though if you do this to use system values as address operands
this probably isn't what you need. (FWIW using consts or using (uniform)
system values for addressing could potentially help llvmpipe/gallivm if
implemented properly - this is because with temp/addr reg all such
indirect lookups need gather (which are expensive) as the address
operand is never uniform (albeit it might be possible llvm may recognize
it in some cases if it actually is uniform).)

Roland


Am 29.09.2017 um 14:25 schrieb Marek Olšák:
> Hi,
> 
> This series removes the limitation that only ADDR registers are
> allowed as address operands. Any 1D register can be an address
> operand (IN, OUT, TEMP, SV, CONST reading from the first buffer slot).
> 
> Requirements:
> - The address operand must be integer.
> - The address operand must be a 1D register (with the exception of
>   CONST that is allowed not to specify the second index in this case).
>   2D registers aren't allowed, because TGSI doesn't support 2D
>   registers as address operands.
> - The address operand must not use indirect indexing within itself.
> 
> If all requirements are met, UARL isn't emitted and the source operand
> of UARL is folded into the instruction where ADDR would normally be
> used.
> 
> The use case that we primarily care about is to get SV[i].x in address
> operands to help us generate better code in radeonsi.
> 
> Please review.
> 
> Thanks,
> Marek
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