[Mesa-dev] [PATCH 5/5] intel: activate the gl_BaseVertex lowering
Antia Puentes
apuentes at igalia.com
Sat Apr 28 12:09:22 UTC 2018
Surplus code related to the basevertex is removed.
The Vertex Elements contain now:
* VE 1: <firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is_indexed_draw, 0, 0>
Also fixes unreachable message.
Fixes OpenGL CTS tests:
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters
Fixes Piglit tests:
* arb_shader_draw_parameters-drawid-indirect baseinstance
* arb_shader_draw_parameters-basevertex
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
---
src/intel/compiler/brw_compiler.c | 3 ++-
src/intel/compiler/brw_compiler.h | 1 -
src/intel/compiler/brw_fs_nir.cpp | 8 ++++----
src/intel/compiler/brw_nir.c | 5 +----
src/intel/compiler/brw_vec4.cpp | 7 +------
src/mesa/drivers/dri/i965/brw_draw.c | 8 ++------
src/mesa/drivers/dri/i965/brw_draw_upload.c | 5 +----
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 -
8 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index d5f483798a9..6480dbefbf6 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -45,7 +45,8 @@
.lower_device_index_to_zero = true, \
.native_integers = true, \
.use_interpolated_input_intrinsics = true, \
- .vertex_id_zero_based = true
+ .vertex_id_zero_based = true, \
+ .lower_base_vertex = true
#define COMMON_SCALAR_OPTIONS \
.lower_pack_half_2x16 = true, \
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index e3bf535a519..8b4e6fe2e29 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -977,7 +977,6 @@ struct brw_vs_prog_data {
bool uses_vertexid;
bool uses_instanceid;
- bool uses_basevertex;
bool uses_is_indexed_draw;
bool uses_firstvertex;
bool uses_baseinstance;
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 22beb0e00d1..02aaf144019 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -112,10 +112,10 @@ emit_system_values_block(nir_block *block, fs_visitor *v)
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
case nir_intrinsic_load_vertex_id:
- unreachable("should be lowered by lower_vertex_id().");
+ case nir_intrinsic_load_base_vertex:
+ unreachable("should be lowered by nir_lower_system_values().");
case nir_intrinsic_load_vertex_id_zero_base:
- case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_is_indexed_draw:
case nir_intrinsic_load_first_vertex:
case nir_intrinsic_load_instance_id:
@@ -2420,10 +2420,10 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld,
switch (instr->intrinsic) {
case nir_intrinsic_load_vertex_id:
- unreachable("should be lowered by lower_vertex_id()");
+ case nir_intrinsic_load_base_vertex:
+ unreachable("should be lowered by nir_lower_system_values()");
case nir_intrinsic_load_vertex_id_zero_base:
- case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_instance_id:
case nir_intrinsic_load_base_instance:
case nir_intrinsic_load_draw_id: {
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index a624deb6d2a..9998c59586e 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -238,8 +238,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
*/
const bool has_sgvs =
nir->info.system_values_read &
- (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
- BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
+ (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
@@ -261,7 +260,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
- case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_first_vertex:
case nir_intrinsic_load_base_instance:
case nir_intrinsic_load_vertex_id_zero_base:
@@ -280,7 +278,6 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_intrinsic_set_base(load, num_inputs);
switch (intrin->intrinsic) {
- case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_first_vertex:
nir_intrinsic_set_component(load, 0);
break;
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 898df90225f..4464a913988 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2825,8 +2825,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
* incoming vertex attribute. So, add an extra slot.
*/
if (shader->info.system_values_read &
- (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
- BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
+ (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
@@ -2840,10 +2839,6 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
nr_attribute_slots++;
}
- if (shader->info.system_values_read &
- BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX))
- prog_data->uses_basevertex = true;
-
if (shader->info.system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))
prog_data->uses_is_indexed_draw = true;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 09199c30453..ffa814e1e8a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -825,16 +825,12 @@ brw_draw_single_prim(struct gl_context *ctx,
const struct brw_vs_prog_data *vs_prog_data =
brw_vs_prog_data(brw->vs.base.prog_data);
if (prim_id > 0) {
- const bool uses_firstvertex =
- vs_prog_data->uses_basevertex ||
- vs_prog_data->uses_firstvertex;
-
const bool uses_draw_parameters =
- uses_firstvertex ||
+ vs_prog_data->uses_firstvertex ||
vs_prog_data->uses_baseinstance;
if ((uses_draw_parameters && prim->is_indirect) ||
- (uses_firstvertex &&
+ (vs_prog_data->uses_firstvertex &&
brw->draw.params.firstvertex != new_firstvertex) ||
(vs_prog_data->uses_baseinstance &&
brw->draw.params.gl_baseinstance != new_baseinstance))
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 55566a7de44..b1be269ca91 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -704,11 +704,8 @@ brw_prepare_shader_draw_parameters(struct brw_context *brw)
const struct brw_vs_prog_data *vs_prog_data =
brw_vs_prog_data(brw->vs.base.prog_data);
- const bool uses_firstvertex =
- vs_prog_data->uses_basevertex || vs_prog_data->uses_firstvertex;
-
/* For non-indirect draws, upload the shader draw parameters */
- if ((uses_firstvertex || vs_prog_data->uses_baseinstance) &&
+ if ((vs_prog_data->uses_firstvertex || vs_prog_data->uses_baseinstance) &&
brw->draw.draw_params_bo == NULL) {
brw_upload_data(&brw->upload,
&brw->draw.params, sizeof(brw->draw.params), 4,
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 093954054fc..b1867c1a1cc 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -541,7 +541,6 @@ genX(emit_vertices)(struct brw_context *brw)
const bool uses_draw_params =
vs_prog_data->uses_firstvertex ||
- vs_prog_data->uses_basevertex ||
vs_prog_data->uses_baseinstance;
const bool uses_derived_draw_params =
--
2.14.1
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