[Mesa-dev] [PATCH 08/18] radeonsi: inline load_fetch_args

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 .../drivers/radeonsi/si_shader_tgsi_mem.c     | 67 ++++++++-----------
 1 file changed, 28 insertions(+), 39 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 68ef9f6d8d0..e7ba17048a7 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -338,58 +338,20 @@ static void buffer_append_args(
 	emit_data->args[emit_data->arg_count++] = offset; /* voffset */
 	if (!atomic) {
 		emit_data->args[emit_data->arg_count++] =
 			force_glc ||
 			inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
 			i1true : i1false; /* glc */
 	}
 	emit_data->args[emit_data->arg_count++] = i1false; /* slc */
 }
 
-static void load_fetch_args(
-		struct lp_build_tgsi_context * bld_base,
-		struct lp_build_emit_data * emit_data)
-{
-	struct si_shader_context *ctx = si_shader_context(bld_base);
-	const struct tgsi_full_instruction * inst = emit_data->inst;
-	unsigned target = inst->Memory.Texture;
-	LLVMValueRef rsrc;
-
-	emit_data->dst_type = ctx->v4f32;
-
-	if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
-		   inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
-		LLVMValueRef offset;
-		LLVMValueRef tmp;
-
-		bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
-		rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
-
-		tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
-		offset = ac_to_integer(&ctx->ac, tmp);
-
-		buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
-				   offset, false, false);
-	} else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
-		   tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
-		image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
-		image_fetch_coords(bld_base, inst, 1, rsrc, &emit_data->args[1]);
-
-		if (target == TGSI_TEXTURE_BUFFER) {
-			buffer_append_args(ctx, emit_data, rsrc, emit_data->args[1],
-					   ctx->i32_0, false, false);
-		} else {
-			emit_data->args[0] = rsrc;
-		}
-	}
-}
-
 static void load_emit_buffer(struct si_shader_context *ctx,
 			     struct lp_build_emit_data *emit_data,
 			     bool can_speculate, bool allow_smem)
 {
 	const struct tgsi_full_instruction *inst = emit_data->inst;
 	uint writemask = inst->Dst[0].Register.WriteMask;
 	uint count = util_last_bit(writemask);
 	LLVMValueRef *args = emit_data->args;
 
 	/* Don't use SMEM for shader buffer loads, because LLVM doesn't
@@ -529,20 +491,48 @@ static void load_emit(
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	const struct tgsi_full_instruction * inst = emit_data->inst;
 	const struct tgsi_shader_info *info = &ctx->shader->selector->info;
 	bool can_speculate = false;
 
 	if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
 		load_emit_memory(ctx, emit_data);
 		return;
 	}
 
+	if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
+	    inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
+		LLVMValueRef offset, tmp, rsrc;
+
+		bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
+		rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
+
+		tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
+		offset = ac_to_integer(&ctx->ac, tmp);
+
+		buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
+				   offset, false, false);
+	} else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
+		   tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
+		LLVMValueRef rsrc;
+		unsigned target = inst->Memory.Texture;
+
+		image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
+		image_fetch_coords(bld_base, inst, 1, rsrc, &emit_data->args[1]);
+
+		if (target == TGSI_TEXTURE_BUFFER) {
+			buffer_append_args(ctx, emit_data, rsrc, emit_data->args[1],
+					   ctx->i32_0, false, false);
+		} else {
+			emit_data->args[0] = rsrc;
+		}
+	}
+
 	if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
 		load_emit_buffer(ctx, emit_data, true, true);
 		return;
 	}
 
 	if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
 		ac_build_waitcnt(&ctx->ac, VM_CNT);
 
 	can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
 			  is_oneway_access_only(inst, info,
@@ -1838,21 +1828,20 @@ void si_shader_context_init_mem(struct si_shader_context *ctx)
 	bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
 	bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
 	bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
 	bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
 	bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
 	bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
 	bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
 
 	bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
 
-	bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
 	bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
 	bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
 	bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
 	bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
 
 	tmpl.fetch_args = atomic_fetch_args;
 	tmpl.emit = atomic_emit;
 	bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
 	bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
 	bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
-- 
2.17.1