[Mesa-dev] [PATCH v2 21.5/22 (was 18/22)] intel: Use TXS for image_size when we have a typed surface

[Kenneth Graunke]

On Wednesday, August 29, 2018 10:12:59 AM PDT Jason Ekstrand wrote:
> ---
>  src/intel/compiler/brw_eu_defines.h           |  2 ++
>  src/intel/compiler/brw_fs_generator.cpp       | 23 +++++++++---
>  src/intel/compiler/brw_fs_nir.cpp             | 35 +++++++++++++++++++
>  .../compiler/brw_nir_lower_image_load_store.c | 15 ++++++++
>  src/intel/compiler/brw_shader.cpp             |  3 ++
>  5 files changed, 74 insertions(+), 4 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
> index 883616d6bab..52957882b10 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -354,6 +354,8 @@ enum opcode {
>     SHADER_OPCODE_SAMPLEINFO,
>     SHADER_OPCODE_SAMPLEINFO_LOGICAL,
>  
> +   SHADER_OPCODE_IMAGE_SIZE,
> +
>     /**
>      * Combines multiple sources of size 1 into a larger virtual GRF.
>      * For example, parameters for a send-from-GRF message.  Or, updating
> diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
> index d40ce2ce0d7..cb402cd4e75 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ b/src/intel/compiler/brw_fs_generator.cpp
> @@ -958,6 +958,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
>           }
>           break;
>        case SHADER_OPCODE_TXS:
> +      case SHADER_OPCODE_IMAGE_SIZE:
>  	 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
>  	 break;
>        case SHADER_OPCODE_TXD:
> @@ -1126,10 +1127,19 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
>        }
>     }
>  
> -   uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
> -         inst->opcode == SHADER_OPCODE_TG4_OFFSET)
> -         ? prog_data->binding_table.gather_texture_start
> -         : prog_data->binding_table.texture_start;
> +   uint32_t base_binding_table_index;
> +   switch (inst->opcode) {
> +   case SHADER_OPCODE_TG4:
> +   case SHADER_OPCODE_TG4_OFFSET:
> +      base_binding_table_index = prog_data->binding_table.gather_texture_start;
> +      break;
> +   case SHADER_OPCODE_IMAGE_SIZE:
> +      base_binding_table_index = prog_data->binding_table.image_start;
> +      break;
> +   default:
> +      base_binding_table_index = prog_data->binding_table.texture_start;
> +      break;
> +   }
>  
>     if (surface_index.file == BRW_IMMEDIATE_VALUE &&
>         sampler_index.file == BRW_IMMEDIATE_VALUE) {
> @@ -2114,6 +2124,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
>        case SHADER_OPCODE_SAMPLEINFO:
>  	 generate_tex(inst, dst, src[0], src[1], src[2]);
>  	 break;
> +
> +      case SHADER_OPCODE_IMAGE_SIZE:
> +         generate_tex(inst, dst, src[0], src[1], brw_imm_ud(0));
> +         break;
> +
>        case FS_OPCODE_DDX_COARSE:
>        case FS_OPCODE_DDX_FINE:
>           generate_ddx(inst, dst, src[0]);
> diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
> index aaba0e2a693..2fef050f81a 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -3918,6 +3918,41 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>        break;
>     }
>  
> +   case nir_intrinsic_image_size: {
> +      /* Unlike the [un]typed load and store opcodes, the TXS that this turns
> +       * into will handle the binding table index for us in the geneerator.
> +       */
> +      fs_reg image = retype(get_nir_src_imm(instr->src[0]),
> +                            BRW_REGISTER_TYPE_UD);
> +      image = bld.emit_uniformize(image);
> +
> +      /* Since the image size is always uniform, we can just emit a SIMD8
> +       * query instruction and splat the result out.
> +       */
> +      const fs_builder ubld = bld.exec_all().group(8, 0);

Ah good, you remembered the exec_all().  Matt just reminded me about it.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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