[Mesa-dev] [PATCH] intel/genxml: add FAULT_REG for Gen10/11

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 src/intel/genxml/gen10.xml | 33 +++++++++++++++++++++++++++++++++
 src/intel/genxml/gen11.xml | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 541e4405716..819a807691a 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3627,6 +3627,39 @@
     <field name="Per Sample Blend Opt Disable Mask"  start="27" end="27" type="bool"/>
   </register>
 
+  <register name="FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Invalid PTE Fault" value="0"/>
+      <value name="Invalid PDE Fault" value="1"/>
+      <value name="Invalid PDPE Fault" value="2"/>
+      <value name="Invalid PML4E Fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="11" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Engine ID" start="12" end="16" type="uint">
+      <value name="GFX" value="0"/>
+      <value name="MFX0" value="1"/>
+      <value name="MFX1" value="2"/>
+      <value name="VEBX" value="3"/>
+      <value name="BLT" value="4"/>
+      <value name="GUC" value="5"/>
+      <value name="GAM" value="7"/>
+      <value name="VDBOX2" value="9"/>
+      <value name="VDBOX3" value="10"/>
+      <value name="VEBOX1" value="11"/>
+      <value name="VDBOX4" value="17"/>
+      <value name="VDBOX5" value="18"/>
+      <value name="VEBOX2" value="19"/>
+      <value name="VDBOX6" value="25"/>
+      <value name="VDBOX7" value="26"/>
+      <value name="VEBOX3" value="27"/>
+    </field>
+  </register>
+
   <register name="CS_DEBUG_MODE2" length="1" num="0x20d8">
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1b3befbbfc9..c10477fda6b 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3625,6 +3625,39 @@
     <field name="Per Sample Blend Opt Disable Mask"  start="27" end="27" type="bool"/>
   </register>
 
+  <register name="FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Invalid PTE Fault" value="0"/>
+      <value name="Invalid PDE Fault" value="1"/>
+      <value name="Invalid PDPE Fault" value="2"/>
+      <value name="Invalid PML4E Fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="11" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Engine ID" start="12" end="16" type="uint">
+      <value name="GFX" value="0"/>
+      <value name="MFX0" value="1"/>
+      <value name="MFX1" value="2"/>
+      <value name="VEBX" value="3"/>
+      <value name="BLT" value="4"/>
+      <value name="GUC" value="5"/>
+      <value name="GAM" value="7"/>
+      <value name="VDBOX2" value="9"/>
+      <value name="VDBOX3" value="10"/>
+      <value name="VEBOX1" value="11"/>
+      <value name="VDBOX4" value="17"/>
+      <value name="VDBOX5" value="18"/>
+      <value name="VEBOX2" value="19"/>
+      <value name="VDBOX6" value="25"/>
+      <value name="VDBOX7" value="26"/>
+      <value name="VEBOX3" value="27"/>
+    </field>
+  </register>
+
   <register name="CS_DEBUG_MODE2" length="1" num="0x20d8">
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
-- 
2.18.0