[Mesa-dev] [PATCH 28/59] intel/compiler: set correct precision fields for 3-source float instructions

[Iago Toral Quiroga]

Source0 and Destination extract the floating-point precision automatically
from the SrcType and DstType instruction fields respectively when they are
set to types :F or :HF. For Source1 and Source2 operands, we use the new
1-bit fields Src1Type and Src2Type, where 0 means normal precision and 1
means half-precision. Since we always use the type of the destination for
all operands when we emit 3-source instructions, we only need set Src1Type
and Src2Type to 1 when we are emitting a half-precision instruction.
---
 src/intel/compiler/brw_eu_emit.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 2c9fc9a5c7c..66edfb43baf 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -801,6 +801,11 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
           */
          brw_inst_set_3src_a16_src_type(devinfo, inst, dest.type);
          brw_inst_set_3src_a16_dst_type(devinfo, inst, dest.type);
+
+         if (devinfo->gen >= 8 && dest.type == BRW_REGISTER_TYPE_HF) {
+            brw_inst_set_3src_a16_src1_type(devinfo, inst, 1);
+            brw_inst_set_3src_a16_src2_type(devinfo, inst, 1);
+         }
       }
    }
 
-- 
2.17.1