[Mesa-dev] [PATCH 27/59] intel/compiler: allow half-float on 3-source instructions since gen8

[Pohjolainen, Topi]

Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

On Tue, Dec 04, 2018 at 08:16:51AM +0100, Iago Toral Quiroga wrote:
> ---
>  src/intel/compiler/brw_eu_emit.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
> index 5f066d17a1f..2c9fc9a5c7c 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -755,7 +755,8 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
>        assert(dest.type == BRW_REGISTER_TYPE_F  ||
>               dest.type == BRW_REGISTER_TYPE_DF ||
>               dest.type == BRW_REGISTER_TYPE_D  ||
> -             dest.type == BRW_REGISTER_TYPE_UD);
> +             dest.type == BRW_REGISTER_TYPE_UD ||
> +             (dest.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 8));
>        if (devinfo->gen == 6) {
>           brw_inst_set_3src_a16_dst_reg_file(devinfo, inst,
>                                              dest.file == BRW_MESSAGE_REGISTER_FILE);
> -- 
> 2.17.1
> 
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