[Mesa-dev] [PATCH 15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

[Jason Ekstrand]

I haven't checked the HW docs but

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga <itoral at igalia.com> wrote:

> Extended math desn't support half-float on these generations.
> ---
>  src/intel/compiler/brw_nir.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index e0027f5179c..0b3094724c4 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -614,6 +614,8 @@ lower_bit_size_callback(const nir_alu_instr *alu,
> UNUSED void *data)
>     if (alu->dest.dest.ssa.bit_size != 16)
>        return 0;
>
> +   const struct brw_compiler *compiler = (const struct brw_compiler *)
> data;
> +
>     switch (alu->op) {
>     case nir_op_idiv:
>     case nir_op_imod:
> @@ -626,6 +628,15 @@ lower_bit_size_callback(const nir_alu_instr *alu,
> UNUSED void *data)
>     case nir_op_fround_even:
>     case nir_op_ftrunc:
>        return 32;
> +   case nir_op_frcp:
> +   case nir_op_frsq:
> +   case nir_op_fsqrt:
> +   case nir_op_fpow:
> +   case nir_op_fexp2:
> +   case nir_op_flog2:
> +   case nir_op_fsin:
> +   case nir_op_fcos:
> +      return compiler->devinfo->gen < 9 ? 32 : 0;
>     default:
>        return 0;
>     }
> @@ -692,7 +703,7 @@ brw_preprocess_nir(const struct brw_compiler
> *compiler, nir_shader *nir)
>        OPT(nir_opt_large_constants, NULL, 32);
>     }
>
> -   OPT(nir_lower_bit_size, lower_bit_size_callback, NULL);
> +   OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler);
>
>     if (is_scalar) {
>        OPT(nir_lower_load_const_to_scalar);
> --
> 2.17.1
>
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