[Mesa-dev] [PATCH 32/38] ac/nir: store all outputs as f32

[Rhys Perry]

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
---
 src/amd/common/ac_nir_to_llvm.c   | 13 ++++++++-----
 src/amd/vulkan/radv_nir_to_llvm.c | 22 +++++++++-------------
 2 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index fa7b8c70f0..b4418af50a 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2051,7 +2051,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
 		unreachable("unhandle variable mode");
 	}
 	ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
-	return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
+	return ac_build_reinterpret(&ctx->ac, ret, get_def_type(ctx, &instr->dest.ssa));
 }
 
 static void
@@ -2063,7 +2063,7 @@ visit_store_var(struct ac_nir_context *ctx,
 	LLVMValueRef temp_ptr, value;
 	int idx = var->data.driver_location;
 	unsigned comp = var->data.location_frac;
-	LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[1]));
+	LLVMValueRef src = get_src(ctx, instr->src[1]);
 	int writemask = instr->const_index[0];
 	LLVMValueRef indir_index;
 	unsigned const_index;
@@ -2082,6 +2082,11 @@ visit_store_var(struct ac_nir_context *ctx,
 
 	writemask = writemask << comp;
 
+	LLVMTypeRef type = ctx->ac.f32;
+	if (LLVMGetTypeKind(LLVMTypeOf(src)) == LLVMVectorTypeKind)
+		type = LLVMVectorType(ctx->ac.f32, LLVMGetVectorSize(LLVMTypeOf(src)));
+	src = ac_build_reinterpret(&ctx->ac, src, type);
+
 	switch (var->data.mode) {
 	case nir_var_shader_out:
 
@@ -4008,12 +4013,10 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
 		}
 	}
 
-	bool is_16bit = glsl_type_is_16bit(variable->type);
-	LLVMTypeRef type = is_16bit ? ctx->f16 : ctx->f32;
 	for (unsigned i = 0; i < attrib_count; ++i) {
 		for (unsigned chan = 0; chan < 4; chan++) {
 			abi->outputs[ac_llvm_reg_index_soa(output_loc + i, chan)] =
-		                       ac_build_alloca_undef(ctx, type, "");
+		                       ac_build_alloca_undef(ctx, ctx->f32, "");
 		}
 	}
 
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index f114a86018..e5e4637f0d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2340,6 +2340,7 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
 
 	bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
 	if (ctx->stage == MESA_SHADER_FRAGMENT) {
+		bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
 		unsigned index = target - V_008DFC_SQ_EXP_MRT;
 		unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
 		bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
@@ -2456,16 +2457,8 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
 		return;
 	}
 
-	if (is_16bit) {
-		for (unsigned chan = 0; chan < 4; chan++) {
-			values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
-			args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
-		}
-	} else
-		memcpy(&args->out[0], values, sizeof(values[0]) * 4);
-
-	for (unsigned i = 0; i < 4; ++i)
-		args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
+	for (unsigned chan = 0; chan < 4; chan++)
+		args->out[chan] = ac_build_reinterpret(&ctx->ac, values[chan], ctx->ac.f32);
 }
 
 static void
@@ -3172,9 +3165,12 @@ handle_fs_outputs_post(struct radv_shader_context *ctx)
 		if (i < FRAG_RESULT_DATA0)
 			continue;
 
-		for (unsigned j = 0; j < 4; j++)
-			values[j] = ac_to_float(&ctx->ac,
-						radv_load_output(ctx, i, j));
+		for (unsigned j = 0; j < 4; j++) {
+			values[j] = radv_load_output(ctx, i, j);
+			unsigned index = ac_llvm_reg_index_soa(i, 0);
+			LLVMTypeRef new_type = ctx->abi.output_types[index];
+			values[j] = ac_build_reinterpret(&ctx->ac, values[j], new_type);
+		}
 
 		bool ret = si_export_mrt_color(ctx, values,
 					       i - FRAG_RESULT_DATA0,
-- 
2.19.2