[Mesa-dev] [PATCH 5/8] radeonsi: add/update assertions for 32-bit address space

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_buffer_common.c | 15 +++++++++++++--
 src/gallium/drivers/radeonsi/si_descriptors.c   |  6 +++++-
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 2d64eed..2106b9b 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -211,24 +211,35 @@ bool si_alloc_resource(struct si_screen *sscreen,
 		return false;
 	}
 
 	/* Replace the pointer such that if res->buf wasn't NULL, it won't be
 	 * NULL. This should prevent crashes with multiple contexts using
 	 * the same buffer where one of the contexts invalidates it while
 	 * the others are using it. */
 	old_buf = res->buf;
 	res->buf = new_buf; /* should be atomic */
 
-	if (sscreen->info.has_virtual_memory)
+	if (sscreen->info.has_virtual_memory) {
 		res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
-	else
+
+		if (res->flags & RADEON_FLAG_32BIT) {
+			uint64_t start = res->gpu_address;
+			uint64_t last = start + res->bo_size - 1;
+			(void)start;
+			(void)last;
+
+			assert((start >> 32) == sscreen->info.address32_hi);
+			assert((last >> 32) == sscreen->info.address32_hi);
+		}
+	} else {
 		res->gpu_address = 0;
+	}
 
 	pb_reference(&old_buf, NULL);
 
 	util_range_set_empty(&res->valid_buffer_range);
 	res->TC_L2_dirty = false;
 
 	/* Print debug information. */
 	if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
 		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %"PRIu64" bytes\n",
 			res->gpu_address, res->gpu_address + res->buf->size,
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 6d5738b..58aa431 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -181,20 +181,24 @@ static bool si_upload_descriptors(struct si_context *sctx,
 				upload_size);
 	desc->gpu_list = ptr - first_slot_offset / 4;
 
 	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
                             RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
 
 	/* The shader pointer should point to slot 0. */
 	buffer_offset -= first_slot_offset;
 	desc->gpu_address = desc->buffer->gpu_address + buffer_offset;
 
+	assert(desc->buffer->flags & RADEON_FLAG_32BIT);
+	assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi);
+	assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi);
+
 	si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
 	return true;
 }
 
 static void
 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
 {
 	if (!desc->buffer)
 		return;
 
@@ -2070,21 +2074,21 @@ static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
 	radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
 }
 
 static void si_emit_shader_pointer_body(struct si_screen *sscreen,
 					struct radeon_winsys_cs *cs,
 					uint64_t va)
 {
 	radeon_emit(cs, va);
 
 	if (HAVE_32BIT_POINTERS)
-		assert((va >> 32) == sscreen->info.address32_hi);
+		assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
 	else
 		radeon_emit(cs, va >> 32);
 }
 
 static void si_emit_shader_pointer(struct si_context *sctx,
 				   struct si_descriptors *desc,
 				   unsigned sh_base)
 {
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 	unsigned sh_offset = sh_base + desc->shader_userdata_offset;
-- 
2.7.4