[Mesa-dev] [PATCH v2] intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.

[Kenneth Graunke]

On Wednesday, June 6, 2018 6:39:19 PM PDT Kenneth Graunke wrote:
> +/**
> + * See vf_invalidate_for_vb_48b_transitions in genX_state_upload.c.
> + */
> +static void
> +blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
> +                                           const struct blorp_address *addrs,
> +                                           unsigned num_vbs)
> +{
> +#if GEN_GEN >= 8
> +   struct brw_context *brw = batch->driver_batch;
> +   bool need_invalidate = false;
> +
> +   for (unsigned i = 0; i < num_vbs; i++) {
> +      struct brw_bo *bo = addrs[i].buffer;
> +      uint16_t high_bits =
> +         bo && (bo->kflags & EXEC_OBJECT_PINNED) ? bo->gtt_offset >> 32u : 0;
> +
> +      if (high_bits != brw->vb.last_bo_high_bits[i]) {

Jason noticed that I botched this again...I added need_invalidate = true
here so it actually does something.

I've gone ahead and pushed this a bit early, since it enabled me to push
the rest of my softpin series and Jordan was blocked on that happening.

> +         brw->vb.last_bo_high_bits[i] = high_bits;
> +      }
> +   }
> +
> +   if (need_invalidate) {
> +      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE);
> +   }
> +#endif
> +}
> +
>  #if GEN_GEN >= 8
>  static struct blorp_address
>  blorp_get_workaround_page(struct blorp_batch *batch)
> 

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