[Mesa-dev] [PATCH 8/8] radeonsi: ignore PIPE_RESOURCE_FLAG_MAP_COHERENT

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

We treat coherent and non-coherent buffers the same.

And move external_usage for better packing.
---
 src/gallium/drivers/radeonsi/si_buffer.c | 3 +--
 src/gallium/drivers/radeonsi/si_pipe.h   | 6 +++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index 0546fa9d336..5bd95bffc17 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -135,22 +135,21 @@ void si_init_resource_fields(struct si_screen *sscreen,
 	case PIPE_USAGE_IMMUTABLE:
 	default:
 		/* Not listing GTT here improves performance in some
 		 * apps. */
 		res->domains = RADEON_DOMAIN_VRAM;
 		res->flags |= RADEON_FLAG_GTT_WC;
 		break;
 	}
 
 	if (res->b.b.target == PIPE_BUFFER &&
-	    res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
-			      PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
+	    res->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
 		/* Use GTT for all persistent mappings with older
 		 * kernels, because they didn't always flush the HDP
 		 * cache before CS execution.
 		 *
 		 * Write-combined CPU mappings are fine, the kernel
 		 * ensures all CPU writes finish before the GPU
 		 * executes a command stream.
 		 *
 		 * radeon doesn't have good BO move throttling, so put all
 		 * persistent buffers into GTT to prevent VRAM CPU page faults.
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index eb0c226ed79..5ff762296fc 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -209,26 +209,26 @@ struct r600_resource {
 	 * Any hw block which doesn't use or bypasses TC L2 should check this
 	 * flag and flush the cache before using the buffer.
 	 *
 	 * For example, TC L2 must be flushed if a buffer which has been
 	 * modified by a shader store instruction is about to be used as
 	 * an index buffer. The reason is that VGT DMA index fetching doesn't
 	 * use TC L2.
 	 */
 	bool				TC_L2_dirty;
 
-	/* Whether the resource has been exported via resource_get_handle. */
-	unsigned			external_usage; /* PIPE_HANDLE_USAGE_* */
-
 	/* Whether this resource is referenced by bindless handles. */
 	bool				texture_handle_allocated;
 	bool				image_handle_allocated;
+
+	/* Whether the resource has been exported via resource_get_handle. */
+	unsigned			external_usage; /* PIPE_HANDLE_USAGE_* */
 };
 
 struct r600_transfer {
 	struct threaded_transfer	b;
 	struct r600_resource		*staging;
 	unsigned			offset;
 };
 
 struct r600_cmask_info {
 	uint64_t offset;
-- 
2.17.1