[Mesa-dev] [PATCH 04/13] i965/draw: Fix adding the stencil bo to the depth cache

[Pohjolainen, Topi]

On Tue, Jun 12, 2018 at 12:21:56PM -0700, Nanley Chery wrote:
> Fix the case where only stencil writes are enabled on a depth stencil

Isn't this an issue even when depth writes are enabled? Both would add the
same bo to cache?

> texture. Found by inspection.
> 
> ---
> 
> I'm looking into writing a test for this.
> 
>  src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
> index 271456e0f7d..71461d7b0a7 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -623,10 +623,10 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
>     }
>  
>     if (stencil_irb && brw->stencil_write_enabled) {
> -      brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
>        struct intel_mipmap_tree *stencil_mt =
>           stencil_irb->mt->stencil_mt != NULL ?
>           stencil_irb->mt->stencil_mt : stencil_irb->mt;
> +      brw_depth_cache_add_bo(brw, stencil_mt->bo);
>        intel_miptree_finish_write(brw, stencil_mt, stencil_irb->mt_level,
>                                   stencil_irb->mt_layer,
>                                   stencil_irb->layer_count, ISL_AUX_USAGE_NONE);
> -- 
> 2.17.0
> 
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