[Mesa-dev] [PATCH v4 3/7] i965: pipecontrol: allow NULL bo for writing registers

[Lionel Landwerlin]

When doing a LRI Post Sync operation, you can put the register offset
in the lower 32bits of the address but won't need a BO.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 1b89e55c396..874e9f0a9e8 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -179,6 +179,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
       OUT_BATCH(flags);
       if (bo) {
          OUT_RELOC64(bo, RELOC_WRITE, offset);
+      } else if ((flags & PIPE_CONTROL_LRI_WRITE_IMMEDIATE) != 0) {
+         OUT_BATCH(offset);
+         OUT_BATCH(0);
       } else {
          OUT_BATCH(0);
          OUT_BATCH(0);
@@ -210,6 +213,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
       OUT_BATCH(flags);
       if (bo) {
          OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, gen6_gtt | offset);
+      } else if (devinfo->gen >= 7 &&
+                 (flags & PIPE_CONTROL_LRI_WRITE_IMMEDIATE) != 0) {
+         OUT_BATCH(offset);
       } else {
          OUT_BATCH(0);
       }
-- 
2.17.1