[Mesa-dev] [PATCH 01/16] radeonsi: work around a GPU hang due to broken indirect indexing in LLVM

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing"
Cc: 18.1 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/si_get.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index d4e0eab187d..c31ab43cb42 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -487,20 +487,29 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
 
 	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 		/* TODO: Indirect indexing of GS inputs is unimplemented. */
 		if (shader == PIPE_SHADER_GEOMETRY)
 			return 0;
 
 		if (shader == PIPE_SHADER_VERTEX &&
 		    !sscreen->llvm_has_working_vgpr_indexing)
 			return 0;
 
+		/* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
+		 * This means we don't support INTERP instructions with
+		 * indirect indexing on inputs.
+		 */
+		if (shader == PIPE_SHADER_FRAGMENT &&
+		    !sscreen->llvm_has_working_vgpr_indexing &&
+		    HAVE_LLVM < 0x0700)
+			return 0;
+
 		/* TCS and TES load inputs directly from LDS or offchip
 		 * memory, so indirect indexing is always supported.
 		 * PS has to support indirect indexing, because we can't
 		 * lower that to TEMPs for INTERP instructions.
 		 */
 		return 1;
 
 	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 		return sscreen->llvm_has_working_vgpr_indexing ||
 		       /* TCS stores outputs directly to memory. */
-- 
2.17.0