[Mesa-dev] [PATCH 02/16] ac: enable both RBs on Kaveri

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

This can result in 2x increase in performance on non-harvested Kaveris.
---
 src/amd/common/ac_gpu_info.c                      | 8 ++++++--
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 031fd183b6f..da54e5f8b4a 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -309,21 +309,26 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->uvd_enc_supported =
 		uvd_enc.available_rings ? true : false;
 	info->has_userptr = true;
 	info->has_syncobj = has_syncobj(fd);
 	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 	info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 	info->has_ctx_priority = info->drm_minor >= 22;
 	/* TODO: Enable this once the kernel handles it efficiently. */
 	info->has_local_buffers = info->drm_minor >= 20 &&
 				  !info->has_dedicated_vram;
+
 	info->num_render_backends = amdinfo->rb_pipes;
+	/* The value returned by the kernel driver was wrong. */
+	if (info->family == CHIP_KAVERI)
+		info->num_render_backends = 2;
+
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 		info->clock_crystal_freq = 1;
 	}
 	info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 	info->gb_addr_config = amdinfo->gb_addr_cfg;
 	if (info->chip_class == GFX9) {
 		info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 		info->pipe_interleave_bytes =
@@ -620,22 +625,21 @@ ac_get_raster_config(struct radeon_info *info,
 			raster_config = 0x00000000;
 		else
 			raster_config = 0x00000002;
 		raster_config_1 = 0x00000000;
 		break;
 	case CHIP_CARRIZO:
 		raster_config = 0x00000002;
 		raster_config_1 = 0x00000000;
 		break;
 	case CHIP_KAVERI:
-		/* KV should be 0x00000002, but that causes problems with radeon */
-		raster_config = 0x00000000; /* 0x00000002 */
+		raster_config = 0x00000002;
 		raster_config_1 = 0x00000000;
 		break;
 	case CHIP_KABINI:
 	case CHIP_MULLINS:
 	case CHIP_STONEY:
 		raster_config = 0x00000000;
 		raster_config_1 = 0x00000000;
 		break;
 	default:
 		fprintf(stderr,
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3ee243adbcc..28811c959fe 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -386,20 +386,24 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
             return false;
     }
     else if (ws->gen >= DRV_R600) {
         uint32_t tiling_config = 0;
 
         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
                                   "num backends",
                                   &ws->info.num_render_backends))
             return false;
 
+	/* The value returned by the kernel driver was wrong. */
+	if (ws->info.family == CHIP_KAVERI)
+		ws->info.num_render_backends = 2;
+
         /* get the GPU counter frequency, failure is not fatal */
         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
                              &ws->info.clock_crystal_freq);
 
         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
                              &tiling_config);
 
         ws->info.r600_num_banks =
             ws->info.chip_class >= EVERGREEN ?
                 4 << ((tiling_config & 0xf0) >> 4) :
-- 
2.17.0