[Mesa-dev] [PATCH 03/14] ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed
Marek Olšák
maraeo at gmail.com
Thu May 3 00:19:41 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/amd/common/ac_gpu_info.c | 2 ++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_compute.c | 4 +---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 +
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index d9b5b4a1960..b2c29f657ca 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -311,20 +311,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
/* TODO: Enable this once the kernel handles it efficiently. */
info->has_local_buffers = info->drm_minor >= 20 &&
!info->has_dedicated_vram;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
+ info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
info->num_render_backends = 2;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
info->clock_crystal_freq = 1;
@@ -460,20 +461,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" drm = %i.%i.%i\n", info->drm_major,
info->drm_minor, info->drm_patchlevel);
printf(" has_userptr = %i\n", info->has_userptr);
printf(" has_syncobj = %u\n", info->has_syncobj);
printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
+ printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 578c3fb7da1..bc6350b5625 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -91,20 +91,21 @@ struct radeon_info {
uint32_t drm_minor;
uint32_t drm_patchlevel;
bool has_userptr;
bool has_syncobj;
bool has_syncobj_wait_for_submit;
bool has_fence_to_handle;
bool has_ctx_priority;
bool has_local_buffers;
bool kernel_flushes_hdp_before_ib;
bool htile_cmask_support_1d_tiling;
+ bool si_TA_CS_BC_BASE_ADDR_allowed;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader engine */
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e95e79c7b46..e20bae0afc4 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -324,23 +324,21 @@ static void si_initialize_compute(struct si_context *sctx)
}
/* Set the pointer to border colors. */
bc_va = sctx->border_color_buffer->gpu_address;
if (sctx->chip_class >= CIK) {
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
} else {
- if (sctx->screen->info.drm_major == 3 ||
- (sctx->screen->info.drm_major == 2 &&
- sctx->screen->info.drm_minor >= 48)) {
+ if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
bc_va >> 8);
}
}
sctx->cs_shader_state.emitted_program = NULL;
sctx->cs_shader_state.initialized = true;
}
static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index d0d7e15803b..b06e18127d1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -529,20 +529,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
*/
ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
+ ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.0
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