[Mesa-dev] [PATCH 04/14] ac/gpu_info: add has_bo_metadata

Marek Olšák maraeo at gmail.com
Thu May 3 00:19:42 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_gpu_info.c                      | 2 ++
 src/amd/common/ac_gpu_info.h                      | 1 +
 src/gallium/drivers/radeonsi/si_texture.c         | 3 +--
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 +
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index b2c29f657ca..85c739ca343 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -312,20 +312,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_syncobj = has_syncobj(fd);
 	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 	info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 	info->has_ctx_priority = info->drm_minor >= 22;
 	/* TODO: Enable this once the kernel handles it efficiently. */
 	info->has_local_buffers = info->drm_minor >= 20 &&
 				  !info->has_dedicated_vram;
 	info->kernel_flushes_hdp_before_ib = true;
 	info->htile_cmask_support_1d_tiling = true;
 	info->si_TA_CS_BC_BASE_ADDR_allowed = true;
+	info->has_bo_metadata = true;
 
 	info->num_render_backends = amdinfo->rb_pipes;
 	/* The value returned by the kernel driver was wrong. */
 	if (info->family == CHIP_KAVERI)
 		info->num_render_backends = 2;
 
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 		info->clock_crystal_freq = 1;
@@ -462,20 +463,21 @@ void ac_print_gpu_info(struct radeon_info *info)
 	       info->drm_minor, info->drm_patchlevel);
 	printf("    has_userptr = %i\n", info->has_userptr);
 	printf("    has_syncobj = %u\n", info->has_syncobj);
 	printf("    has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
 	printf("    has_fence_to_handle = %u\n", info->has_fence_to_handle);
 	printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
 	printf("    has_local_buffers = %u\n", info->has_local_buffers);
 	printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
 	printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
 	printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
+	printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
 	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
 	printf("    max_se = %i\n", info->max_se);
 	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
 	printf("Render backend info:\n");
 	printf("    num_render_backends = %i\n", info->num_render_backends);
 	printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index bc6350b5625..340c368bda3 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -92,20 +92,21 @@ struct radeon_info {
 	uint32_t                    drm_patchlevel;
 	bool                        has_userptr;
 	bool                        has_syncobj;
 	bool                        has_syncobj_wait_for_submit;
 	bool                        has_fence_to_handle;
 	bool                        has_ctx_priority;
 	bool                        has_local_buffers;
 	bool                        kernel_flushes_hdp_before_ib;
 	bool                        htile_cmask_support_1d_tiling;
 	bool                        si_TA_CS_BC_BASE_ADDR_allowed;
+	bool                        has_bo_metadata;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
 	/* Render backends (color + depth blocks). */
 	uint32_t                    r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index f38d4721331..3601c2806bc 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -601,22 +601,21 @@ static void si_query_opaque_metadata(struct si_screen *sscreen,
 	struct pipe_resource *res = &rtex->buffer.b.b;
 	static const unsigned char swizzle[] = {
 		PIPE_SWIZZLE_X,
 		PIPE_SWIZZLE_Y,
 		PIPE_SWIZZLE_Z,
 		PIPE_SWIZZLE_W
 	};
 	uint32_t desc[8], i;
 	bool is_array = util_texture_is_array(res->target);
 
-	/* DRM 2.x.x doesn't support this. */
-	if (sscreen->info.drm_major != 3)
+	if (!sscreen->info.has_bo_metadata)
 		return;
 
 	assert(rtex->dcc_separate_buffer == NULL);
 	assert(rtex->surface.fmask_size == 0);
 
 	/* Metadata image format format version 1:
 	 * [0] = 1 (metadata format identifier)
 	 * [1] = (VENDOR_ID << 16) | PCI_ID
 	 * [2:9] = image descriptor for the whole resource
 	 *         [2] is always 0, because the base address is cleared
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index b06e18127d1..358c45fed1c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -530,20 +530,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 				     (ws->info.family == CHIP_HAWAII &&
 				      ws->accel_working2 < 3);
     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
     ws->info.ib_start_alignment = 4096;
     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
     /* HTILE is broken with 1D tiling on old kernels and CIK. */
     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
+    ws->info.has_bo_metadata = false;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 
     return true;
 }
 
 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 {
     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 
-- 
2.17.0



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