[Mesa-dev] [PATCH 06/14] ac/gpu_info: add has_eqaa_surface_allocator

Marek Olšák maraeo at gmail.com
Thu May 3 00:19:44 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_gpu_info.c                      | 4 +++-
 src/amd/common/ac_gpu_info.h                      | 3 ++-
 src/gallium/drivers/radeonsi/si_pipe.c            | 2 +-
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 +
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 94dfff77ac1..232a8bcd523 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -315,20 +315,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_ctx_priority = info->drm_minor >= 22;
 	/* TODO: Enable this once the kernel handles it efficiently. */
 	info->has_local_buffers = info->drm_minor >= 20 &&
 				  !info->has_dedicated_vram;
 	info->kernel_flushes_hdp_before_ib = true;
 	info->htile_cmask_support_1d_tiling = true;
 	info->si_TA_CS_BC_BASE_ADDR_allowed = true;
 	info->has_bo_metadata = true;
 	info->has_gpu_reset_status_query = true;
 	info->has_gpu_reset_counter_query = false;
+	info->has_eqaa_surface_allocator = true;
 
 	info->num_render_backends = amdinfo->rb_pipes;
 	/* The value returned by the kernel driver was wrong. */
 	if (info->family == CHIP_KAVERI)
 		info->num_render_backends = 2;
 
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 		info->clock_crystal_freq = 1;
@@ -453,35 +454,36 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    ce_fw_version = %i\n", info->ce_fw_version);
 	printf("    ce_fw_feature = %i\n", info->ce_fw_feature);
 
 	printf("Multimedia info:\n");
 	printf("    has_hw_decode = %u\n", info->has_hw_decode);
 	printf("    uvd_enc_supported = %u\n", info->uvd_enc_supported);
 	printf("    uvd_fw_version = %u\n", info->uvd_fw_version);
 	printf("    vce_fw_version = %u\n", info->vce_fw_version);
 	printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
 
-	printf("Kernel info:\n");
+	printf("Kernel & winsys capabilities:\n");
 	printf("    drm = %i.%i.%i\n", info->drm_major,
 	       info->drm_minor, info->drm_patchlevel);
 	printf("    has_userptr = %i\n", info->has_userptr);
 	printf("    has_syncobj = %u\n", info->has_syncobj);
 	printf("    has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
 	printf("    has_fence_to_handle = %u\n", info->has_fence_to_handle);
 	printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
 	printf("    has_local_buffers = %u\n", info->has_local_buffers);
 	printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
 	printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
 	printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
 	printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
 	printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
 	printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
+	printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
 	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
 	printf("    max_se = %i\n", info->max_se);
 	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
 	printf("Render backend info:\n");
 	printf("    num_render_backends = %i\n", info->num_render_backends);
 	printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index f5b74579ef1..f8e4adf0d41 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -79,36 +79,37 @@ struct radeon_info {
 	uint32_t                    ce_fw_version;
 	uint32_t                    ce_fw_feature;
 
 	/* Multimedia info. */
 	bool                        has_hw_decode;
 	bool                        uvd_enc_supported;
 	uint32_t                    uvd_fw_version;
 	uint32_t                    vce_fw_version;
 	uint32_t                    vce_harvest_config;
 
-	/* Kernel info. */
+	/* Kernel & winsys capabilities. */
 	uint32_t                    drm_major; /* version */
 	uint32_t                    drm_minor;
 	uint32_t                    drm_patchlevel;
 	bool                        has_userptr;
 	bool                        has_syncobj;
 	bool                        has_syncobj_wait_for_submit;
 	bool                        has_fence_to_handle;
 	bool                        has_ctx_priority;
 	bool                        has_local_buffers;
 	bool                        kernel_flushes_hdp_before_ib;
 	bool                        htile_cmask_support_1d_tiling;
 	bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 	bool                        has_bo_metadata;
 	bool                        has_gpu_reset_status_query;
 	bool                        has_gpu_reset_counter_query;
+	bool                        has_eqaa_surface_allocator;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
 	/* Render backends (color + depth blocks). */
 	uint32_t                    r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index bf61b0071e7..fe0a20ba6cd 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1075,21 +1075,21 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 
 	 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
 	 * Constraints:
 	 *     s >= z >= c (ignoring this only wastes memory)
 	 *     s = [2..16]
 	 *     z = [2..8]
 	 *     c = [2..8]
 	 *
 	 * Only MSAA color and depth buffers are overriden.
 	 */
-	if (sscreen->info.drm_major == 3) {
+	if (sscreen->info.has_eqaa_surface_allocator) {
 		const char *eqaa = debug_get_option("EQAA", NULL);
 		unsigned s,z,f;
 
 		if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
 			sscreen->eqaa_force_coverage_samples = s;
 			sscreen->eqaa_force_z_samples = z;
 			sscreen->eqaa_force_color_samples = f;
 		}
 	}
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index eb783e846ac..f2646b2ad32 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -533,20 +533,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
     ws->info.ib_start_alignment = 4096;
     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
     /* HTILE is broken with 1D tiling on old kernels and CIK. */
     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
     ws->info.has_bo_metadata = false;
     ws->info.has_gpu_reset_status_query = false;
     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
+    ws->info.has_eqaa_surface_allocator = false;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 
     return true;
 }
 
 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 {
     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 
-- 
2.17.0



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