[Mesa-dev] [PATCH 05/14] radeonsi: clean up the reset status query implementation

Marek Olšák maraeo at gmail.com
Thu May 3 00:19:43 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_gpu_info.c                  |  4 +++
 src/amd/common/ac_gpu_info.h                  |  2 ++
 src/gallium/drivers/radeonsi/si_get.c         |  5 ++-
 src/gallium/drivers/radeonsi/si_pipe.c        | 36 +++++++++----------
 .../winsys/radeon/drm/radeon_drm_winsys.c     |  2 ++
 5 files changed, 26 insertions(+), 23 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 85c739ca343..94dfff77ac1 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -313,20 +313,22 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 	info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 	info->has_ctx_priority = info->drm_minor >= 22;
 	/* TODO: Enable this once the kernel handles it efficiently. */
 	info->has_local_buffers = info->drm_minor >= 20 &&
 				  !info->has_dedicated_vram;
 	info->kernel_flushes_hdp_before_ib = true;
 	info->htile_cmask_support_1d_tiling = true;
 	info->si_TA_CS_BC_BASE_ADDR_allowed = true;
 	info->has_bo_metadata = true;
+	info->has_gpu_reset_status_query = true;
+	info->has_gpu_reset_counter_query = false;
 
 	info->num_render_backends = amdinfo->rb_pipes;
 	/* The value returned by the kernel driver was wrong. */
 	if (info->family == CHIP_KAVERI)
 		info->num_render_backends = 2;
 
 	info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 	if (!info->clock_crystal_freq) {
 		fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 		info->clock_crystal_freq = 1;
@@ -464,20 +466,22 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    has_userptr = %i\n", info->has_userptr);
 	printf("    has_syncobj = %u\n", info->has_syncobj);
 	printf("    has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
 	printf("    has_fence_to_handle = %u\n", info->has_fence_to_handle);
 	printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
 	printf("    has_local_buffers = %u\n", info->has_local_buffers);
 	printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
 	printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
 	printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
 	printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
+	printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
+	printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
 	printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
 	printf("    max_se = %i\n", info->max_se);
 	printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
 	printf("Render backend info:\n");
 	printf("    num_render_backends = %i\n", info->num_render_backends);
 	printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 340c368bda3..f5b74579ef1 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -93,20 +93,22 @@ struct radeon_info {
 	bool                        has_userptr;
 	bool                        has_syncobj;
 	bool                        has_syncobj_wait_for_submit;
 	bool                        has_fence_to_handle;
 	bool                        has_ctx_priority;
 	bool                        has_local_buffers;
 	bool                        kernel_flushes_hdp_before_ib;
 	bool                        htile_cmask_support_1d_tiling;
 	bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 	bool                        has_bo_metadata;
+	bool                        has_gpu_reset_status_query;
+	bool                        has_gpu_reset_counter_query;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
 	/* Render backends (color + depth blocks). */
 	uint32_t                    r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index c31ab43cb42..cd3e63c73d7 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -196,23 +196,22 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_FBFETCH:
 		return 1;
 
 	case PIPE_CAP_TGSI_BALLOT:
 		return HAVE_LLVM >= 0x0500;
 
 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 		return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 
 	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-		return (sscreen->info.drm_major == 2 &&
-			sscreen->info.drm_minor >= 43) ||
-		       sscreen->info.drm_major == 3;
+		return sscreen->info.has_gpu_reset_status_query ||
+		       sscreen->info.has_gpu_reset_counter_query;
 
 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
 		/* 2D tiling on CIK is supported since DRM 2.35.0 */
 		return sscreen->info.chip_class < CIK ||
 		       (sscreen->info.drm_major == 2 &&
 			sscreen->info.drm_minor >= 35) ||
 		       sscreen->info.drm_major == 3;
 
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
                 return SI_MAP_BUFFER_ALIGNMENT;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d5ca34474f0..bf61b0071e7 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -279,39 +279,39 @@ static void si_destroy_context(struct pipe_context *context)
 	_mesa_hash_table_destroy(sctx->img_handles, NULL);
 
 	util_dynarray_fini(&sctx->resident_tex_handles);
 	util_dynarray_fini(&sctx->resident_img_handles);
 	util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
 	util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
 	util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
 	FREE(sctx);
 }
 
-static enum pipe_reset_status
-si_amdgpu_get_reset_status(struct pipe_context *ctx)
+static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
 
-	return sctx->ws->ctx_query_reset_status(sctx->ctx);
-}
+	if (sctx->screen->info.has_gpu_reset_status_query)
+		return sctx->ws->ctx_query_reset_status(sctx->ctx);
 
-static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
-{
-	struct si_context *sctx = (struct si_context *)ctx;
-	unsigned latest = sctx->ws->query_value(sctx->ws,
-						  RADEON_GPU_RESET_COUNTER);
+	if (sctx->screen->info.has_gpu_reset_counter_query) {
+		unsigned latest = sctx->ws->query_value(sctx->ws,
+							RADEON_GPU_RESET_COUNTER);
+
+		if (sctx->gpu_reset_counter == latest)
+			return PIPE_NO_RESET;
 
-	if (sctx->gpu_reset_counter == latest)
-		return PIPE_NO_RESET;
+		sctx->gpu_reset_counter = latest;
+		return PIPE_UNKNOWN_CONTEXT_RESET;
+	}
 
-	sctx->gpu_reset_counter = latest;
-	return PIPE_UNKNOWN_CONTEXT_RESET;
+	return PIPE_NO_RESET;
 }
 
 static void si_set_device_reset_callback(struct pipe_context *ctx,
 					   const struct pipe_device_reset_callback *cb)
 {
 	struct si_context *sctx = (struct si_context *)ctx;
 
 	if (cb)
 		sctx->device_reset_callback = *cb;
 	else
@@ -404,27 +404,26 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 	sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 
 	slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
 	slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
 
 	sctx->ws = sscreen->ws;
 	sctx->family = sscreen->info.family;
 	sctx->chip_class = sscreen->info.chip_class;
 
-	if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 43) {
-		sctx->b.get_device_reset_status = si_get_reset_status;
+	if (sscreen->info.has_gpu_reset_counter_query) {
 		sctx->gpu_reset_counter =
-				sctx->ws->query_value(sctx->ws,
-							RADEON_GPU_RESET_COUNTER);
+			sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
 	}
 
+	sctx->b.get_device_reset_status = si_get_reset_status;
 	sctx->b.set_device_reset_callback = si_set_device_reset_callback;
 
 	si_init_context_texture_functions(sctx);
 	si_init_query_functions(sctx);
 
 	if (sctx->chip_class == CIK ||
 	    sctx->chip_class == VI ||
 	    sctx->chip_class == GFX9) {
 		sctx->eop_bug_scratch = r600_resource(
 			pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
@@ -461,23 +460,20 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 	sctx->ctx = sctx->ws->ctx_create(sctx->ws);
 	if (!sctx->ctx)
 		goto fail;
 
 	if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
 		sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
 						       (void*)si_flush_dma_cs,
 						       sctx);
 	}
 
-	if (sscreen->info.drm_major == 3)
-		sctx->b.get_device_reset_status = si_amdgpu_get_reset_status;
-
 	si_init_buffer_functions(sctx);
 	si_init_clear_functions(sctx);
 	si_init_blit_functions(sctx);
 	si_init_compute_functions(sctx);
 	si_init_cp_dma_functions(sctx);
 	si_init_debug_functions(sctx);
 	si_init_msaa_functions(sctx);
 	si_init_streamout_functions(sctx);
 
 	if (sscreen->info.has_hw_decode) {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 358c45fed1c..eb783e846ac 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -531,20 +531,22 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
 				     (ws->info.family == CHIP_HAWAII &&
 				      ws->accel_working2 < 3);
     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
     ws->info.ib_start_alignment = 4096;
     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
     /* HTILE is broken with 1D tiling on old kernels and CIK. */
     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
     ws->info.has_bo_metadata = false;
+    ws->info.has_gpu_reset_status_query = false;
+    ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 
     return true;
 }
 
 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 {
     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 
-- 
2.17.0



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