[Mesa-dev] [RFC PATCH] mesa/st/cb_clear: in st_Clear also validate the render state (needed by virgl)

[Gert Wollny]

A number of  CTS tests from the dEQP-GLES3.functional.rasterizer_discard.* subset
fail when the tests are run in a batch, because the GL_RASTERIZER_DISCARD state
is enabled after running glClear and the disabled state issed after a number of draw
commands is not properly send to the host.

This happens because in virgl the render state is not validated (and updated on the host)
when clear is run. With this patch  the render state is explicitely updated in st_Clear
thereby fixing these failures.

Signed-off-by: Gert Wollny <gert.wollny at collabora.com>

---
The reason why I send this as a RFC is that I'm well aware of the fact that the drivers
that use the blitter to execute a clear do already implicitely call st_validate_state for
ST_PIPELINE_RENDER because the blitter does so.  Unfortunetely, I haven't found yet how I
can issue this call from virgl_clear, because I don't see how I can access the rasterer
state from there, but maybe someone has a pointer for me?

Many thanks,
Gert

PS: I don't have mesa-git commit rights.

---
 src/mesa/state_tracker/st_cb_clear.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c
index fbc577a370..8f8295ea6c 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -377,6 +377,7 @@ st_Clear(struct gl_context *ctx, GLbitfield mask)
 
    /* This makes sure the pipe has the latest scissor, etc values */
    st_validate_state(st, ST_PIPELINE_CLEAR);
+   st_validate_state(st, ST_PIPELINE_RENDER);
 
    if (mask & BUFFER_BITS_COLOR) {
       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
-- 
2.16.1