[Mesa-dev] [PATCH v2 00/18] anv: add shaderInt16 support
Clayton Craft
clayton.a.craft at intel.com
Thu May 3 18:44:49 UTC 2018
Quoting Iago Toral Quiroga (2018-04-30 07:18:08)
> This version addresses the feedback received to v1, which includes moving the
> bit-size lowering pass from intel to core NIR (patch 8) and a separate patch
> to add Intel's specific configuration for int16 (patch 9), and then it also
> adds a few things that were missing in the first version, namely, a fix for
> 16-bit comparisons to emit 32-bit booleans (patch 10 -a patch to optimize the
> resulting code will come later-) and 16-bit pack/unpack which is needed for
> 16-bit bitcasts (patches 11-15).
>
> Patches 6-15 need review, the rest (1-5 and 16-18), have already been reviewed
> and don't have changes.
>
> A branch with the series is available for testing in the
> 'itoral/shaderInt16ForReview_v2' branch of the Igalia mesa repository at
> github:
>
> https://github.com/Igalia/mesa/tree/itoral/shaderInt16ForReview_v2
>
> Iago Toral Quiroga (16):
> intel/compiler: fix isign for 16-bit integers
> i965/compiler: handle conversion to smaller type in the lowering pass
> for that
> intel/compiler: implement conversion between float/int 16-bit types
> intel/compiler: implement conversions from 16-bit int/float to bool
> intel/compiler: fix brw_imm_w for negative 16-bit integers
> compiler/nir: add a lowering pass to convert the bit size of ALU
> operations
> intel/compiler: lower some 16-bit integer operations to 32-bit
> intel/compiler: fix 16-bit comparisons
> nir: add opcodes for 16-bit packing and unpacking
> nir/lower_64bit_packing: extend the pass to handle packing from / to
> 16-bit.
> compiler/lower_64bit_packing: rename the pass to be more generic
> compiler/spirv: implement 16-bit bitcasts
> intel/compiler: implement 16-bit pack/unpack opcodes
> compiler/spirv: add implementation to check for SpvCapabilityInt16
> support
> anv/pipeline: support SpvCapabilityInt16 in gen8+
> anv/device: expose shaderInt16 support in gen8+
>
> Jose Maria Casanova Crespo (2):
> intel/compiler: implement nir_instr_type_load_const for 16-bit
> constants
> intel/compiler: fix brw_negate_immediate for 16-bit types
>
> src/amd/vulkan/radv_shader.c | 2 +-
> src/compiler/Makefile.sources | 3 +-
> src/compiler/nir/meson.build | 3 +-
> src/compiler/nir/nir.h | 8 +-
> src/compiler/nir/nir_lower_bit_size.c | 127 +++++++++++++++++++++
> ...r_lower_64bit_packing.c => nir_lower_packing.c} | 70 ++++++++++--
> src/compiler/nir/nir_opcodes.py | 19 +++
> src/compiler/shader_info.h | 1 +
> src/compiler/spirv/spirv_to_nir.c | 4 +-
> src/compiler/spirv/vtn_alu.c | 31 +++--
> src/intel/compiler/brw_fs_lower_conversions.cpp | 5 +-
> src/intel/compiler/brw_fs_nir.cpp | 100 +++++++++++-----
> src/intel/compiler/brw_nir.c | 23 +++-
> src/intel/compiler/brw_reg.h | 2 +-
> src/intel/compiler/brw_shader.cpp | 11 +-
> src/intel/vulkan/anv_device.c | 2 +-
> src/intel/vulkan/anv_pipeline.c | 1 +
> src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
> 18 files changed, 356 insertions(+), 58 deletions(-)
> create mode 100644 src/compiler/nir/nir_lower_bit_size.c
> rename src/compiler/nir/{nir_lower_64bit_packing.c => nir_lower_packing.c} (56%)
>
> --
> 2.14.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Since this patch series was merged, we are seeing a number of failures in CI on
BSW, GLK, and BXT platforms:
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64
fdo bug: #106389
Output from tests is:
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64:
INTEL-MESA: error: ../src/intel/vulkan/anv_queue.c:275:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/genX_state.c:247:
VK_ERROR_OUT_OF_HOST_MEMORY
deqp-vk: ../src/intel/compiler/brw_fs_generator.cpp:2482: int
fs_generator::generate_code(const cfg_t*, int): Assertion `validated' failed.
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64:
INTEL-MESA: warning: ../src/intel/vulkan/anv_device.c:1034: FINISHME: Implement
pop-free point clipping
INTEL-MESA: debug: anv_GetPhysicalDeviceProperties2: ignored VkStructureType
1000145002
INTEL-MESA: debug: anv_GetPhysicalDeviceProperties2: ignored VkStructureType
1000145002
INTEL-MESA: error: ../src/intel/vulkan/anv_device.c:2602:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_image.c:581:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_cmd_buffer.c:194:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_batch_chain.c:273:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_batch_chain.c:67:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_batch_chain.c:75:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_batch_chain.c:67:
VK_ERROR_OUT_OF_HOST_MEMORY
../src/intel/isl/isl.c:683: FINISHME:
../src/intel/isl/isl.c:isl_calc_phys_level0_extent_sa: YUV format
deqp-vk: ../src/intel/compiler/brw_fs_generator.cpp:2482: int
fs_generator::generate_code(const cfg_t*, int): Assertion `validated' failed.
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64:
INTEL-MESA: error: ../src/intel/vulkan/anv_device.c:2602:
VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/anv_image.c:581:
VK_ERROR_OUT_OF_HOST_MEMORY
deqp-vk: ../src/intel/compiler/brw_fs_generator.cpp:2482: int
fs_generator::generate_code(const cfg_t*, int): Assertion `validated' failed.
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