[Mesa-dev] [PATCH 10/10] i965: perf: enable Icelake metrics

Lionel Landwerlin lionel.g.landwerlin at intel.com
Fri May 4 14:52:53 UTC 2018


Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources        |  3 ++-
 src/mesa/drivers/dri/i965/brw_performance_query.c | 10 ++++++++--
 src/mesa/drivers/dri/i965/meson.build             |  1 +
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 5e53d874d88..55df6ce90f7 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -174,4 +174,5 @@ i965_oa_xml_FILES = \
 	brw_oa_glk.xml \
 	brw_oa_cflgt2.xml \
 	brw_oa_cflgt3.xml \
-	brw_oa_cnl.xml
+	brw_oa_cnl.xml \
+	brw_oa_icl.xml
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 77d23133ad4..f549db34e92 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1993,17 +1993,21 @@ compute_topology_builtins(struct brw_context *brw)
    brw->perfquery.sys_vars.eu_threads_count =
       brw->perfquery.sys_vars.n_eus * devinfo->num_thread_per_eu;
 
-   /* At the moment the subslice mask builtin has groups of 3bits for each
+   /* The subslice mask builtin contains bits for all slices. Prior to Gen11
+    * it had groups of 3bits for each slice, on Gen11 it's 8bits for each
     * slice.
     *
     * Ideally equations would be updated to have a slice/subslice query
     * function/operator.
     */
    brw->perfquery.sys_vars.subslice_mask = 0;
+
+   int bits_per_subslice = devinfo->gen == 11 ? 8 : 3;
+
    for (int s = 0; s < util_last_bit(devinfo->slice_masks); s++) {
       for (int ss = 0; ss < (devinfo->subslice_slice_stride * 8); ss++) {
          if (gen_device_info_subslice_available(devinfo, s, ss))
-            brw->perfquery.sys_vars.subslice_mask |= 1UL << (s * 3 + ss);
+            brw->perfquery.sys_vars.subslice_mask |= 1UL << (s * bits_per_subslice + ss);
       }
    }
 }
@@ -2148,6 +2152,8 @@ get_register_queries_function(const struct gen_device_info *devinfo)
    }
    if (devinfo->is_cannonlake)
       return brw_oa_register_queries_cnl;
+   if (devinfo->gen == 11)
+      return brw_oa_register_queries_icl;
 
    return NULL;
 }
diff --git a/src/mesa/drivers/dri/i965/meson.build b/src/mesa/drivers/dri/i965/meson.build
index a2c1896fecb..0ef0bb9e69e 100644
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -160,6 +160,7 @@ i965_hw_metrics = [
   'cflgt2', 'cflgt3',
   'bxt', 'glk',
   'cnl',
+  'icl',
 ]
 
 i965_hw_metrics_xml_files = []
-- 
2.17.0



More information about the mesa-dev mailing list