[Mesa-dev] [PATCH 08/16] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Nicolai Hähnle]

On 02.05.2018 06:00, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
> 
> ---
>   src/amd/common/ac_surface.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index b2af1f70b69..341a7854fe5 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -841,22 +841,27 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>   		 *
>   		 * "dcc_alignment * 4" was determined by trial and error.
>   		 */
>   		surf->dcc_size = align64(surf->surf_size >> 8,
>   					 surf->dcc_alignment * 4);
>   	}
>   
>   	/* Make sure HTILE covers the whole miptree, because the shader reads
>   	 * TC-compatible HTILE even for levels where it's disabled by DB.
>   	 */
> -	if (surf->htile_size && config->info.levels > 1)
> -		surf->htile_size *= 2;
> +	if (surf->htile_size && config->info.levels > 1 &&
> +	    surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
> +		surf->htile_size =
> +			surf->surf_size * 4 / (8 * 8 * surf->bpe *
> +					       MAX2(1, config->info.samples));

Can you explain this formula? In particular where the 4 comes from?

Thanks,
Nicolai


> +		surf->htile_size = align64(surf->htile_size, surf->htile_alignment);
> +	}
>   
>   	surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
>   	surf->is_displayable = surf->is_linear ||
>   			       surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
>   			       surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
>   	return 0;
>   }
>   
>   /* This is only called when expecting a tiled layout. */
>   static int
> 


-- 
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Aber vergiss niemals, wie sie sein sollte.