[Mesa-dev] [PATCH 08/16] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Marek Olšák]

On Tue, May 8, 2018 at 3:06 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:

> On 02.05.2018 06:00, Marek Olšák wrote:
>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> ---
>>   src/amd/common/ac_surface.c | 9 +++++++--
>>   1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
>> index b2af1f70b69..341a7854fe5 100644
>> --- a/src/amd/common/ac_surface.c
>> +++ b/src/amd/common/ac_surface.c
>> @@ -841,22 +841,27 @@ static int gfx6_compute_surface(ADDR_HANDLE
>> addrlib,
>>                  *
>>                  * "dcc_alignment * 4" was determined by trial and error.
>>                  */
>>                 surf->dcc_size = align64(surf->surf_size >> 8,
>>                                          surf->dcc_alignment * 4);
>>         }
>>         /* Make sure HTILE covers the whole miptree, because the shader
>> reads
>>          * TC-compatible HTILE even for levels where it's disabled by DB.
>>          */
>> -       if (surf->htile_size && config->info.levels > 1)
>> -               surf->htile_size *= 2;
>> +       if (surf->htile_size && config->info.levels > 1 &&
>> +           surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
>> +               surf->htile_size =
>> +                       surf->surf_size * 4 / (8 * 8 * surf->bpe *
>> +                                              MAX2(1,
>> config->info.samples));
>>
>
> Can you explain this formula? In particular where the 4 comes from?
>

Sure.

Definitions (for the whole miptree):
1) surf_size = bpe * samples * num_pixels
2) htile_size = num_pixels * 4 / (8 * 8)

Therefore:
num_pixels = surf_size / (bpe * samples), so:
htile_size = (surf_size / (bpe * samples)) * 4 / (8 * 8)

Marek
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