[Mesa-dev] [PATCH v2 1/2] isl: remove the cache line size alignment requirement

[Jason Ekstrand]

Rb

On February 19, 2019 06:06:41 Samuel Iglesias Gonsálvez 
<siglesias at igalia.com> wrote:

> The cacheline size was a requirement for using the BLT engine, which
> we don't use anymore except for a few things on old HW, so we drop it.
>
> Fixes CTS's CL#3500 test:
>
> dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
>
> Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
> ---
> src/intel/isl/isl.c | 14 --------------
> 1 file changed, 14 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index eaaa28014a3..5c34efb9a13 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -1381,20 +1381,6 @@ isl_calc_row_pitch(const struct isl_device *dev,
>    uint32_t alignment_B =
>       isl_calc_row_pitch_alignment(surf_info, tile_info);
>
> -   /* If pitch isn't given and it can be chosen freely, align it by cache line
> -    * allowing one to use blit engine on the surface.
> -    */
> -   if (surf_info->row_pitch_B == 0 && tile_info->tiling == 
> ISL_TILING_LINEAR) {
> -      /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
> -       *
> -       *    "Base address of the destination surface: X=0, Y=0. Lower 32bits
> -       *    of the 48bit addressing. When Src Tiling is enabled (Bit_15
> -       *    enabled), this address must be 4KB-aligned. When Tiling is not
> -       *    enabled, this address should be CL (64byte) aligned."
> -       */
> -      alignment_B = MAX2(alignment_B, 64);
> -   }
> -
>    const uint32_t min_row_pitch_B =
>       isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
>                              alignment_B);
> --
> 2.19.1
>
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