[Mesa-dev] [PATCH v2 2/2] isl: the display engine requires 64B alignment for linear surfaces
lionel.g.landwerlin at intel.com
Fri Feb 22 11:46:46 UTC 2019
Pushed with the PRM quote, thanks!
On 22/02/2019 06:16, Samuel Iglesias Gonsálvez wrote:
> Lionel, are you going to push it with this quote? I can add it
> On Thu, 2019-02-21 at 13:41 +0000, Lionel Landwerlin wrote:
>> On 21/02/2019 13:30, Chris Wilson wrote:
>>> Quoting Lionel Landwerlin (2019-02-21 12:57:09)
>>>> I did not find the PRM bit that says it must be 64b aligned, but
>>>> I can
>>>> see that's what i915 checks.
>>>> Chris: If you have a pointer to it, I could add the quote.
>>> In amongst the register specs,
>>> For Linear memory, this field specifies the stride in chunks of 64
>>> bytes (1 cache line).
>> Thanks a lot!
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